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Changed udelay in delay_tsc to be more be more considerate of single 

processor environments.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Hamish Guthrie 2005-08-17 04:48:17 +00:00
parent 3d291aa6a2
commit e251c42197
2 changed files with 11 additions and 0 deletions
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4
src/cpu/x86/tsc/delay_tsc.c
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@ -159,7 +159,11 @@ void udelay(unsigned us)
count = rdtscll(); count = rdtscll();
stop = clocks + count; stop = clocks + count;
while(stop > count) { while(stop > count) {
#ifdef CONFIG_SMP
#if CONFIG_SMP == 1
cpu_relax(); cpu_relax();
#endif
#endif
count = rdtscll(); count = rdtscll();
} }
} }

7
src/mainboard/eaglelion/5bcm/Options.lb
View File

@ -37,6 +37,8 @@ uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD uses TTYS0_BAUD
uses TTYS0_BASE uses TTYS0_BASE
uses TTYS0_LCS uses TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
## ROM_SIZE is the size of boot ROM that this board will use. ## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024 default ROM_SIZE = 256*1024
@ -60,6 +62,11 @@ default HAVE_MP_TABLE=0
## ##
default HAVE_HARD_RESET=0 default HAVE_HARD_RESET=0
## Delay timer options
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## ##
## Build code to export a programmable irq routing table ## Build code to export a programmable irq routing table
## ##