GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/ironlake: Move out HECI remainders into southbridge 

Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.

Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2022-02-14 13:04:34 +01:00 committed by Felix Held
parent fdb0294846
commit e2531ffaa8
5 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/northbridge/intel/ironlake/early_init.c
View File

@ -106,10 +106,6 @@ void ironlake_early_initialization(int chipset_type)
early_cpu_init(); early_cpu_init();
pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Magic for S3 resume. Must be done early. */ /* Magic for S3 resume. Must be done early. */
if (s3_resume) { if (s3_resume) {
mchbar_clrsetbits32(0x1e8, 1, 6); mchbar_clrsetbits32(0x1e8, 1, 6);

2
src/northbridge/intel/ironlake/ironlake.h
View File

@ -3,8 +3,6 @@
#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
#define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
/* /*
* D1:F0 PEG * D1:F0 PEG
*/ */

5
src/southbridge/intel/ibexpeak/early_pch.c
View File

@ -2,6 +2,7 @@
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/smbus_host.h> #include <device/smbus_host.h>
#include <northbridge/intel/ironlake/ironlake.h> #include <northbridge/intel/ironlake/ironlake.h>
@ -46,6 +47,10 @@ void ibexpeak_setup_bars(void)
/* halt timer */ /* halt timer */
outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, " done.\n");
pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
} }
void early_pch_init(void) void early_pch_init(void)

1
src/southbridge/intel/ibexpeak/pch.h
View File

@ -22,6 +22,7 @@
/* TODO Make sure these don't get changed by stage2 */ /* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500 #define DEFAULT_PMBASE 0x0500
#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/rcba.h>

1
src/southbridge/intel/ibexpeak/setup_heci_uma.c
View File

@ -6,6 +6,7 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <northbridge/intel/ironlake/ironlake.h> #include <northbridge/intel/ironlake/ironlake.h>
#include <southbridge/intel/ibexpeak/me.h> #include <southbridge/intel/ibexpeak/me.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include <types.h> #include <types.h>
#define HECIDEV PCI_DEV(0, 0x16, 0) #define HECIDEV PCI_DEV(0, 0x16, 0)