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MMCONF_SUPPORT: Consolidate resource registration 

Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17695
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-12-02 08:56:05 +02:00
parent 3d15e10aef
commit e25b5ef39f
25 changed files with 132 additions and 276 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/device/device_util.c
View File

@ -888,6 +888,26 @@ void fixed_mem_resource(device_t dev, unsigned long index,
resource->flags |= type;
}
void mmconf_resource_init(struct resource *resource, resource_t base,
int buses)
{
resource->base = base;
resource->size = buses * MiB;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR "
"0x%08lx-0x%08lx.\n", (unsigned long)(resource->base),
(unsigned long)(resource->base + resource->size));
}
void mmconf_resource(struct device *dev, unsigned long index)
{
struct resource *resource = new_resource(dev, index);
mmconf_resource_init(resource, CONFIG_MMCONF_BASE_ADDRESS,
CONFIG_MMCONF_BUS_NUMBER);
}
void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;

3
src/include/device/device.h
View File

@ -234,6 +234,9 @@ void pci_domain_scan_bus(struct device *dev);
void fixed_mem_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek, unsigned long type);
void mmconf_resource_init(struct resource *res, resource_t base, int buses);
void mmconf_resource(struct device *dev, unsigned long index);
void scan_smbus(device_t bus);
void scan_static_bus(device_t bus);
void scan_lpc_bus(device_t bus);

21
src/northbridge/amd/agesa/family10/northbridge.c
View File

@ -424,6 +424,13 @@ static void amdfam10_read_resources(device_t dev)
amdfam10_link_read_bases(dev, nodeid, link->link_num);
}
}
/*
* This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
mmconf_resource(dev, 0xc0010058);
}
static void amdfam10_set_resource(device_t dev, struct resource *resource,
@ -530,6 +537,11 @@ static void amdfam10_set_resources(device_t dev)
assign_resources(bus);
}
}
res = find_resource(dev, 0xc0010058);
if (res) {
report_resource_stored(dev, res, " <mmconfig>");
}
}
static void mcf0_control_init(struct device *dev)
@ -1096,19 +1108,10 @@ static void cpu_bus_init(device_t dev)
static void cpu_bus_read_resources(device_t dev)
{
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void cpu_bus_set_resources(device_t dev)
{
struct resource *resource = find_resource(dev, 0xc0010058);
if (resource) {
report_resource_stored(dev, resource, " <mmconfig>");
}
pci_dev_set_resources(dev);
}

13
src/northbridge/amd/agesa/family12/northbridge.c
View File

@ -300,6 +300,14 @@ static void read_resources(device_t dev)
amdfam12_link_read_bases(dev, nodeid, link->link_num);
}
}
/*
* This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
mmconf_resource(dev, 0xc0010058);
printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
}
@ -649,11 +657,6 @@ static void cpu_bus_read_resources(device_t dev)
{
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
}

6
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -302,11 +302,7 @@ static void nb_read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

6
src/northbridge/amd/agesa/family15/northbridge.c
View File

@ -326,11 +326,7 @@ static void nb_read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

6
src/northbridge/amd/agesa/family15rl/northbridge.c
View File

@ -326,11 +326,7 @@ static void read_resources(struct device *dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)

6
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -325,11 +325,7 @@ static void nb_read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

6
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -325,11 +325,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the APIC_CLUSTER.
*/
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

9
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -741,14 +741,7 @@ static void amdfam10_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
/* We have MMCONF_SUPPORT, create the resource window. */
struct resource *res = new_resource(dev, 0xc0010058);
res->base = CONFIG_MMCONF_BASE_ADDRESS;
res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */
res->align = log2(res->size);
res->gran = log2(res->size);
res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */
res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmconf_resource(dev, 0xc0010058);
/* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);

11
src/northbridge/amd/pi/00630F01/northbridge.c
View File

@ -309,15 +309,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
static void enable_mmconf_resource(device_t dev)
{
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void read_resources(device_t dev)
{
u32 nodeid;
@ -335,7 +326,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
enable_mmconf_resource(dev);
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

11
src/northbridge/amd/pi/00660F01/northbridge.c
View File

@ -304,15 +304,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
static void enable_mmconf_resource(device_t dev)
{
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void read_resources(device_t dev)
{
u32 nodeid;
@ -330,7 +321,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
enable_mmconf_resource(dev);
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

11
src/northbridge/amd/pi/00670F00/northbridge.c
View File

@ -304,15 +304,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
static void enable_mmconf_resource(device_t dev)
{
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void read_resources(device_t dev)
{
u32 nodeid;
@ -330,7 +321,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
enable_mmconf_resource(dev);
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

11
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -312,15 +312,6 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
static void enable_mmconf_resource(device_t dev)
{
struct resource *resource = new_resource(dev, 0xc0010058);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void read_resources(device_t dev)
{
u32 nodeid;
@ -338,7 +329,7 @@ static void read_resources(device_t dev)
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
enable_mmconf_resource(dev);
mmconf_resource(dev, 0xc0010058);
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

27
src/northbridge/intel/fsp_rangeley/northbridge.c
View File

@ -57,13 +57,12 @@ int bridge_silicon_revision(void)
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
static int get_pcie_bar(u32 *base, u32 *len)
static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
*len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@ -76,25 +75,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28));
*len = 256 * 1024 * 1024; /* 256MB ECAM range */
return 1;
return 256;
}
static int add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);
resource = new_resource(dev, index++);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
resource = new_resource(dev, index++); /* Local APIC */
resource->base = LAPIC_DEFAULT_BASE;
@ -154,9 +141,19 @@ static void mc_add_dram_resources(device_t dev)
static void mc_read_resources(device_t dev)
{
u32 pcie_config_base;
int buses;
/* Call the normal read_resources */
pci_dev_read_resources(dev);
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
buses = get_pcie_bar(&pcie_config_base);
if (buses) {
struct resource *resource = new_resource(dev, 0xcf);
mmconf_resource_init(resource, pcie_config_base, buses);
}
/* Calculate and add DRAM resources. */
mc_add_dram_resources(dev);
}

46
src/northbridge/intel/fsp_sandybridge/northbridge.c
View File

@ -62,13 +62,12 @@ int bridge_silicon_revision(void)
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
static int get_pcie_bar(u32 *base, u32 *len)
static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
*len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@ -82,16 +81,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
*len = 256 * 1024 * 1024;
return 1;
return 256;
case 1: // 128M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
*len = 128 * 1024 * 1024;
return 1;
return 128;
case 2: // 64M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
*len = 64 * 1024 * 1024;
return 1;
return 64;
}
return 0;
@ -99,21 +95,8 @@ static int get_pcie_bar(u32 *base, u32 *len)
static void add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);
resource = new_resource(dev, index++);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
}
@ -256,24 +239,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
struct resource *resource;
u32 pcie_config_base;
int buses;
pci_dev_read_resources(dev);
/* So, this is one of the big mysteries in the coreboot resource
* allocator. This resource should make sure that the address space
* of the PCIe memory mapped config space bar. But it does not.
*/
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
resource = new_resource(dev, 0xcf);
resource->base = DEFAULT_PCIEXBAR;
resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
resource->flags =
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
(unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
buses = get_pcie_bar(&pcie_config_base);
if (buses) {
struct resource *resource = new_resource(dev, 0xcf);
mmconf_resource_init(resource, pcie_config_base, buses);
}
}
static void mc_set_resources(device_t dev)

10
src/northbridge/intel/i3100/northbridge.c
View File

@ -32,9 +32,6 @@
#include <arch/acpi.h>
static u32 max_bus;
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
@ -139,14 +136,9 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
struct resource *resource;
pci_dev_read_resources(dev);
resource = new_resource(dev, 0xcf);
resource->base = 0xe0000000;
resource->size = max_bus * 4096*256;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmconf_resource(dev, 0xcf);
}
static void mc_set_resources(device_t dev)

45
src/northbridge/intel/i945/northbridge.c
View File

@ -27,13 +27,12 @@
#include <arch/acpi.h>
#include "i945.h"
static int get_pcie_bar(u32 *base, u32 *len)
static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
*len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@ -47,36 +46,18 @@ static int get_pcie_bar(u32 *base, u32 *len)
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
*len = 256 * 1024 * 1024;
return 1;
return 256;
case 1: // 128M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
*len = 128 * 1024 * 1024;
return 1;
return 128;
case 2: // 64M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
*len = 64 * 1024 * 1024;
return 1;
return 64;
}
return 0;
}
static void add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar\n");
resource = new_resource(dev, index++);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
}
static void pci_domain_set_resources(device_t dev)
{
uint32_t pci_tolm;
@ -153,8 +134,6 @@ static void pci_domain_set_resources(device_t dev)
uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10);
mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10);
add_fixed_resources(dev, 7);
assign_resources(dev->link_list);
}
@ -173,19 +152,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
struct resource *resource;
u32 pcie_config_base;
int buses;
pci_dev_read_resources(dev);
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
resource = new_resource(dev, 0xcf);
resource->base = DEFAULT_PCIEXBAR;
resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
resource->flags =
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
(unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
buses = get_pcie_bar(&pcie_config_base);
if (buses) {
struct resource *resource = new_resource(dev, 0xcf);
mmconf_resource_init(resource, pcie_config_base, buses);
}
}
static void mc_set_resources(device_t dev)

4
src/northbridge/intel/nehalem/Kconfig
View File

@ -24,6 +24,10 @@ config NORTHBRIDGE_INTEL_NEHALEM
if NORTHBRIDGE_INTEL_NEHALEM
config MMCONF_BUS_NUMBER
int
default 256
config CBFS_SIZE
hex
default 0x100000

11
src/northbridge/intel/nehalem/northbridge.c
View File

@ -69,11 +69,6 @@ static void add_fixed_resources(struct device *dev, int index)
0xfed1c000-0xfed20000 RCBA
0xfed90000-0xfed94000 IOMMU
0xff800000-0xffffffff ROM. */
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xe0000000;
resource->size = (resource_t) 0x10000000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xfed00000;
@ -98,10 +93,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
}
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
@ -119,6 +110,8 @@ static void mc_read_resources(device_t dev)
pci_dev_read_resources(dev);
mmconf_resource(dev, 0x50);
tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
D0F0_TOUUD);

46
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -61,13 +61,12 @@ int bridge_silicon_revision(void)
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
static int get_pcie_bar(u32 *base, u32 *len)
static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
*len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@ -81,16 +80,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
*len = 256 * 1024 * 1024;
return 1;
return 256;
case 1: // 128M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
*len = 128 * 1024 * 1024;
return 1;
return 128;
case 2: // 64M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
*len = 64 * 1024 * 1024;
return 1;
return 64;
}
return 0;
@ -98,21 +94,8 @@ static int get_pcie_bar(u32 *base, u32 *len)
static void add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);
resource = new_resource(dev, index++);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
mmio_resource(dev, index++, legacy_hole_base_k,
(0xc0000 >> 10) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
@ -276,24 +259,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
struct resource *resource;
u32 pcie_config_base;
int buses;
pci_dev_read_resources(dev);
/* So, this is one of the big mysteries in the coreboot resource
* allocator. This resource should make sure that the address space
* of the PCIe memory mapped config space bar. But it does not.
*/
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
resource = new_resource(dev, 0xcf);
resource->base = DEFAULT_PCIEXBAR;
resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
resource->flags =
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
(unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
buses = get_pcie_bar(&pcie_config_base);
if (buses) {
struct resource *resource = new_resource(dev, 0xcf);
mmconf_resource_init(resource, pcie_config_base, buses);
}
}
static void mc_set_resources(device_t dev)

4
src/northbridge/via/vx900/Kconfig
View File

@ -33,6 +33,10 @@ config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config MMCONF_BUS_NUMBER
int
default 256
config VGA_BIOS_ID
string
default "1106,7122"

5
src/northbridge/via/vx900/northbridge.c
View File

@ -297,10 +297,7 @@ static void vx900_read_resources(device_t dev)
/* Now do the same for our MMCONF
* We always run with MMCONF enabled. We need to access the extended
* config space when configuring PCI-Express links */
res = new_resource(dev, idx++);
res->size = 256 * MiB;
res->base = CONFIG_MMCONF_BASE_ADDRESS;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
mmconf_resource(dev, idx++);
pci_domain_read_resources(dev);
}

27
src/soc/intel/fsp_baytrail/northcluster.c
View File

@ -86,13 +86,12 @@ uint32_t nc_read_top_of_low_memory(void)
return fsp_mem_base;
}
static int get_pcie_bar(u32 *base, u32 *len)
static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
*len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
@ -105,26 +104,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28));
*len = 256 * 1024 * 1024; /* 256MB ECAM range */
return 1;
return 256;
}
static int add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);
resource = new_resource(dev, index++);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
resource = new_resource(dev, index++); /* Local APIC */
resource->base = LAPIC_DEFAULT_BASE;
@ -182,9 +168,18 @@ static void mc_add_dram_resources(device_t dev)
static void nc_read_resources(device_t dev)
{
u32 pcie_config_base;
int buses;
/* Call the normal read_resources */
pci_dev_read_resources(dev);
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
buses = get_pcie_bar(&pcie_config_base);
if (buses) {
struct resource *resource = new_resource(dev, 0xcf);
mmconf_resource_init(resource, pcie_config_base, buses);
}
/* Calculate and add DRAM resources. */
mc_add_dram_resources(dev);

43
src/soc/intel/sch/northbridge.c
View File

@ -27,7 +27,7 @@
#include <arch/acpi.h>
#include "sch.h"
static int get_pcie_bar(u32 *base, u32 *len)
static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
@ -50,18 +50,15 @@ static int get_pcie_bar(u32 *base, u32 *len)
case 0: /* 256MB */
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28));
*len = 256 * 1024 * 1024;
return 1;
return 256;
case 1: /* 128M */
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27));
*len = 128 * 1024 * 1024;
return 1;
return 128;
case 2: /* 64M */
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27) | (1 << 26));
*len = 64 * 1024 * 1024;
return 1;
return 64;
}
return 0;
@ -70,16 +67,6 @@ static int get_pcie_bar(u32 *base, u32 *len)
static void add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar\n");
resource = new_resource(dev, index++);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
printk(BIOS_DEBUG, "Adding CMC shadow area\n");
resource = new_resource(dev, index++);
@ -198,28 +185,20 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev)
{
struct resource *resource;
u32 pcie_config_base;
int buses;
pci_dev_read_resources(dev);
/*
* So, this is one of the big mysteries in the coreboot resource
* allocator. This resource should make sure that the address space
* of the PCIe memory mapped config space bar. But it does not.
*/
/*
* We use 0xcf as an unused index for our PCIe bar so that we find
* it again.
*/
resource = new_resource(dev, 0xcf);
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
get_pcie_bar((u32 *)&resource->base, (u32 *)&resource->size);
printk(BIOS_DEBUG,
"Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
(unsigned long)(resource->base),
(unsigned long)(resource->base + resource->size));
buses = get_pcie_bar(&pcie_config_base);
if (buses) {
struct resource *resource = new_resource(dev, 0xcf);
mmconf_resource_init(resource, pcie_config_base, buses);
}
}
static void mc_set_resources(device_t dev)