baskingridge: rename graysreef to baskingridge
The Grays Reef CRB is deprecated by order of Intel. Basking Ridge is the new hotness. Therefore, rename graysreef to basking ridge. Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I203497e165d8efc99d3438c4c548140a6e9cc649 Reviewed-on: http://review.coreboot.org/2672 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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@ -19,8 +19,8 @@ config BOARD_INTEL_TRUXTON
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bool "EP80579 devkit (Truxton)"
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bool "EP80579 devkit (Truxton)"
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config BOARD_INTEL_XE7501DEVKIT
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config BOARD_INTEL_XE7501DEVKIT
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bool "XE7501devkit"
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bool "XE7501devkit"
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config BOARD_INTEL_GRAYSREEF
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config BOARD_INTEL_BASKING_RIDGE
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bool "Grays Reef CRB"
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bool "Basking Ridge CRB"
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endchoice
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endchoice
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@ -28,7 +28,7 @@ source "src/mainboard/intel/d810e2cb/Kconfig"
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source "src/mainboard/intel/d945gclf/Kconfig"
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source "src/mainboard/intel/d945gclf/Kconfig"
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source "src/mainboard/intel/eagleheights/Kconfig"
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source "src/mainboard/intel/eagleheights/Kconfig"
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source "src/mainboard/intel/emeraldlake2/Kconfig"
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source "src/mainboard/intel/emeraldlake2/Kconfig"
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source "src/mainboard/intel/graysreef/Kconfig"
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source "src/mainboard/intel/baskingridge/Kconfig"
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source "src/mainboard/intel/jarrell/Kconfig"
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source "src/mainboard/intel/jarrell/Kconfig"
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source "src/mainboard/intel/mtarvon/Kconfig"
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source "src/mainboard/intel/mtarvon/Kconfig"
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source "src/mainboard/intel/truxton/Kconfig"
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source "src/mainboard/intel/truxton/Kconfig"
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@ -1,4 +1,4 @@
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if BOARD_INTEL_GRAYSREEF
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if BOARD_INTEL_BASKING_RIDGE
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config BOARD_SPECIFIC_OPTIONS # dummy
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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def_bool y
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@ -20,11 +20,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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default intel/graysreef
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default intel/baskingridge
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config MAINBOARD_PART_NUMBER
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config MAINBOARD_PART_NUMBER
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string
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string
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default "GRAYS REEF"
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default "BASKING RIDGE"
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config MMCONF_BASE_ADDRESS
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config MMCONF_BASE_ADDRESS
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hex
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hex
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@ -42,4 +42,4 @@ config VGA_BIOS_FILE
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string
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string
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default "pci8086,0166.rom"
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default "pci8086,0166.rom"
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endif # BOARD_INTEL_GRAYSREEF
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endif # BOARD_INTEL_BASKING_RIDGE
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@ -17,8 +17,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#ifndef GRAYSREEF_GPIO_H
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#ifndef BASKING_RIDGE_GPIO_H
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#define GRAYSREEF_GPIO_H
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#define BASKING_RIDGE_GPIO_H
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#include "southbridge/intel/lynxpoint/gpio.h"
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#include "southbridge/intel/lynxpoint/gpio.h"
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@ -225,7 +225,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
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.gpio68 = GPIO_LEVEL_HIGH,
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.gpio68 = GPIO_LEVEL_HIGH,
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};
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};
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const struct pch_gpio_map graysreef_gpio_map = {
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const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.direction = &pch_gpio_set1_direction,
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@ -185,7 +185,7 @@ void main(unsigned long bist)
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/* Enable GPIOs */
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/* Enable GPIOs */
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pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
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pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
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pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
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pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
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setup_pch_gpios(&graysreef_gpio_map);
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setup_pch_gpios(&mainboard_gpio_map);
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/* Early Console setup */
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/* Early Console setup */
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console_init();
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console_init();
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@ -17,8 +17,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#ifndef GRAYSREEF_THERMAL_H
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#ifndef BASKING_RIDGE_THERMAL_H
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#define GRAYSREEF_THERMAL_H
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#define BASKING_RIDGE_THERMAL_H
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/* Fan is OFF */
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/* Fan is OFF */
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#define FAN4_THRESHOLD_OFF 0
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#define FAN4_THRESHOLD_OFF 0
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