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soc/amd/*/acpi: factor out common generate_cpu_entries implementation

Browse source 
With the exception of the generate_cppc_entries call, the
implementations of generate_cpu_entries of Picasso, Cezanne, Mendocino,
Phoenix and Glinda are identical, so factor it out and move it to the
common AMD SoC code. Since all SoCs that support CPPC already select the
SOC_AMD_COMMON_BLOCK_ACPI_CPPC Kconfig option, this can be used to only
call generate_cppc_entries for platforms where it is available.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71323d9d071b6f9d82852479b60dc56c24f2b9ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2023-03-07 01:41:56 +01:00
parent a4284b0bd4
commit e266dacaa1
7 changed files with 70 additions and 285 deletions
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59
src/soc/amd/cezanne/acpi.c
View file

@ -184,8 +184,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@ -246,58 +246,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
void generate_cpu_entries(const struct device *device)
{
int logical_cores;
size_t cstate_count, pstate_count, cpu;
acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
uint32_t threads_per_core;
const acpi_addr_t perf_ctrl = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_CTL_REG,
};
const acpi_addr_t perf_sts = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_STS_REG,
};
threads_per_core = get_threads_per_core();
cstate_count = get_cstate_info(cstate_values);
pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
logical_cores = get_cpu_count();
for (cpu = 0; cpu < logical_cores; cpu++) {
acpigen_write_processor_device(cpu);
acpigen_write_pct_package(&perf_ctrl, &perf_sts);
acpigen_write_pss_object(pstate_values, pstate_count);
acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
HW_ALL);
else
acpigen_write_PSD_package(0, logical_cores, SW_ALL);
acpigen_write_PPC(0);
acpigen_write_CST_package(cstate_values, cstate_count);
acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
CSD_HW_ALL, 0);
generate_cppc_entries(cpu);
acpigen_write_processor_device_end();
}
acpigen_write_processor_package("PPKG", 0, logical_cores);
}

59
src/soc/amd/common/block/acpi/cpu_power_state.c
View file

@ -2,6 +2,7 @@
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
#include <amdblocks/cppc.h>
#include <amdblocks/cpu.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
@ -42,7 +43,7 @@ static void write_cstate_entry(acpi_cstate_t *entry, const acpi_cstate_t *data,
}
}
size_t get_cstate_info(acpi_cstate_t *cstate_values)
static size_t get_cstate_info(acpi_cstate_t *cstate_values)
{
size_t i;
size_t cstate_count;
@ -63,3 +64,59 @@ size_t get_cstate_info(acpi_cstate_t *cstate_values)
return i;
}
void generate_cpu_entries(const struct device *device)
{
int logical_cores;
size_t cstate_count, pstate_count, cpu;
acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
uint32_t threads_per_core;
const acpi_addr_t perf_ctrl = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_CTL_REG,
};
const acpi_addr_t perf_sts = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_STS_REG,
};
threads_per_core = get_threads_per_core();
cstate_count = get_cstate_info(cstate_values);
pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
logical_cores = get_cpu_count();
for (cpu = 0; cpu < logical_cores; cpu++) {
acpigen_write_processor_device(cpu);
acpigen_write_pct_package(&perf_ctrl, &perf_sts);
acpigen_write_pss_object(pstate_values, pstate_count);
acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
HW_ALL);
else
acpigen_write_PSD_package(0, logical_cores, SW_ALL);
acpigen_write_PPC(0);
acpigen_write_CST_package(cstate_values, cstate_count);
acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
CSD_HW_ALL, 0);
if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_CPPC))
generate_cppc_entries(cpu);
acpigen_write_processor_device_end();
}
acpigen_write_processor_package("PPKG", 0, logical_cores);
}

3
src/soc/amd/common/block/include/amdblocks/cpu.h
View file

@ -14,7 +14,8 @@ unsigned int get_threads_per_core(void);
void set_cstate_io_addr(void);
void write_resume_eip(void);
size_t get_cstate_info(acpi_cstate_t *cstate_values);
size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values);
const acpi_cstate_t *get_cstate_config_data(size_t *size);
#endif /* AMD_BLOCK_CPU_H */

59
src/soc/amd/glinda/acpi.c
View file

@ -187,8 +187,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@ -249,58 +249,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
void generate_cpu_entries(const struct device *device)
{
int logical_cores;
size_t cstate_count, pstate_count, cpu;
acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
uint32_t threads_per_core;
const acpi_addr_t perf_ctrl = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_CTL_REG,
};
const acpi_addr_t perf_sts = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_STS_REG,
};
threads_per_core = get_threads_per_core();
cstate_count = get_cstate_info(cstate_values);
pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
logical_cores = get_cpu_count();
for (cpu = 0; cpu < logical_cores; cpu++) {
acpigen_write_processor_device(cpu);
acpigen_write_pct_package(&perf_ctrl, &perf_sts);
acpigen_write_pss_object(pstate_values, pstate_count);
acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
HW_ALL);
else
acpigen_write_PSD_package(0, logical_cores, SW_ALL);
acpigen_write_PPC(0);
acpigen_write_CST_package(cstate_values, cstate_count);
acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
CSD_HW_ALL, 0);
generate_cppc_entries(cpu);
acpigen_write_processor_device_end();
}
acpigen_write_processor_package("PPKG", 0, logical_cores);
}

59
src/soc/amd/mendocino/acpi.c
View file

@ -186,8 +186,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@ -248,58 +248,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
void generate_cpu_entries(const struct device *device)
{
int logical_cores;
size_t cstate_count, pstate_count, cpu;
acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
uint32_t threads_per_core;
const acpi_addr_t perf_ctrl = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_CTL_REG,
};
const acpi_addr_t perf_sts = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_STS_REG,
};
threads_per_core = get_threads_per_core();
cstate_count = get_cstate_info(cstate_values);
pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
logical_cores = get_cpu_count();
for (cpu = 0; cpu < logical_cores; cpu++) {
acpigen_write_processor_device(cpu);
acpigen_write_pct_package(&perf_ctrl, &perf_sts);
acpigen_write_pss_object(pstate_values, pstate_count);
acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
HW_ALL);
else
acpigen_write_PSD_package(0, logical_cores, SW_ALL);
acpigen_write_PPC(0);
acpigen_write_CST_package(cstate_values, cstate_count);
acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
CSD_HW_ALL, 0);
generate_cppc_entries(cpu);
acpigen_write_processor_device_end();
}
acpigen_write_processor_package("PPKG", 0, logical_cores);
}

59
src/soc/amd/phoenix/acpi.c
View file

@ -187,8 +187,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@ -249,58 +249,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
void generate_cpu_entries(const struct device *device)
{
int logical_cores;
size_t cstate_count, pstate_count, cpu;
acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
uint32_t threads_per_core;
const acpi_addr_t perf_ctrl = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_CTL_REG,
};
const acpi_addr_t perf_sts = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_STS_REG,
};
threads_per_core = get_threads_per_core();
cstate_count = get_cstate_info(cstate_values);
pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
logical_cores = get_cpu_count();
for (cpu = 0; cpu < logical_cores; cpu++) {
acpigen_write_processor_device(cpu);
acpigen_write_pct_package(&perf_ctrl, &perf_sts);
acpigen_write_pss_object(pstate_values, pstate_count);
acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
HW_ALL);
else
acpigen_write_PSD_package(0, logical_cores, SW_ALL);
acpigen_write_PPC(0);
acpigen_write_CST_package(cstate_values, cstate_count);
acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
CSD_HW_ALL, 0);
generate_cppc_entries(cpu);
acpigen_write_processor_device_end();
}
acpigen_write_processor_package("PPKG", 0, logical_cores);
}

57
src/soc/amd/picasso/acpi.c
View file

@ -188,8 +188,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@ -245,56 +245,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
void generate_cpu_entries(const struct device *device)
{
int logical_cores;
size_t cstate_count, pstate_count, cpu;
acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
uint32_t threads_per_core;
const acpi_addr_t perf_ctrl = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_CTL_REG,
};
const acpi_addr_t perf_sts = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 64,
.addrl = PS_STS_REG,
};
threads_per_core = get_threads_per_core();
cstate_count = get_cstate_info(cstate_values);
pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
logical_cores = get_cpu_count();
for (cpu = 0; cpu < logical_cores; cpu++) {
acpigen_write_processor_device(cpu);
acpigen_write_pct_package(&perf_ctrl, &perf_sts);
acpigen_write_pss_object(pstate_values, pstate_count);
acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
HW_ALL);
else
acpigen_write_PSD_package(0, logical_cores, SW_ALL);
acpigen_write_PPC(0);
acpigen_write_CST_package(cstate_values, cstate_count);
acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
CSD_HW_ALL, 0);
acpigen_write_processor_device_end();
}
acpigen_write_processor_package("PPKG", 0, logical_cores);
}