soc/intel/cannonlake: Add new cannon lake PCH-H support

Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.

- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
  SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.

- Add new device IDs to intel common code respectively.

- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.

- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
  is modified accordingly.

- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.

BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
     are enumerated and cross checked devices ids in serial logs and UEFI shell.

Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/include/device/pci_ids.h

@@ -2690,6 +2690,8 @@
 #define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC	0x9d85
 #define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC	0x9d84
 #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC	0x9d83
+#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370	0xa306
+#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370	0xa30c
 
 /* Intel PCIE device ids  */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1		0x9d10
@@ -2768,6 +2770,31 @@
 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15		0x9db6
 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16		0x9db7
 
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1		0xa338
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2		0xa339
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3		0xa33a
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4		0xa33b
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5		0xa33c
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6		0xa33d
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7		0xa33e
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8		0xa33f
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9		0xa330
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10		0xa331
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11		0xa332
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12		0xa333
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13		0xa334
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14		0xa335
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15		0xa336
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16		0xa337
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17		0xa340
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18		0xa341
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19		0xa342
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20		0xa343
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21		0xa32c
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22		0xa32d
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23		0xa32e
+#define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24		0xa32f
+
 /* Intel SATA device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_U_SATA		0x9d03
 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA		0x9d07
@@ -2787,6 +2814,7 @@
 #define PCI_DEVICE_ID_INTEL_APL_PMC		0x5a94
 #define PCI_DEVICE_ID_INTEL_GLK_PMC		0x3194
 #define PCI_DEVICE_ID_INTEL_CNL_PMC		0x9da1
+#define PCI_DEVICE_ID_INTEL_CNP_H_PMC		0xa321
 
 /* Intel I2C device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_I2C0		0x9d60
@@ -2821,6 +2849,10 @@
 #define PCI_DEVICE_ID_INTEL_CNL_I2C3		0x9deb
 #define PCI_DEVICE_ID_INTEL_CNL_I2C4		0x9dc5
 #define PCI_DEVICE_ID_INTEL_CNL_I2C5		0x9dc6
+#define PCI_DEVICE_ID_INTEL_CNP_H_I2C0		0xa368
+#define PCI_DEVICE_ID_INTEL_CNP_H_I2C1		0xa369
+#define PCI_DEVICE_ID_INTEL_CNP_H_I2C2		0xa36a
+#define PCI_DEVICE_ID_INTEL_CNP_H_I2C3		0xa36b
 
 /* Intel UART device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_UART0		0x9d27
@@ -2843,6 +2875,9 @@
 #define PCI_DEVICE_ID_INTEL_CNL_UART0		0x9da8
 #define PCI_DEVICE_ID_INTEL_CNL_UART1		0x9da9
 #define PCI_DEVICE_ID_INTEL_CNL_UART2		0x9dc7
+#define PCI_DEVICE_ID_INTEL_CNP_H_UART0		0xa328
+#define PCI_DEVICE_ID_INTEL_CNP_H_UART1		0xa329
+#define PCI_DEVICE_ID_INTEL_CNP_H_UART2		0xa347
 
 /* Intel SPI device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_SPI1		0x9d24
@@ -2888,6 +2923,8 @@
 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3		0x5A42
 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4		0x5A4A
 #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT			0x3EA5
+#define PCI_DEVICE_ID_INTEL_CFL_H_GT2			0x3e9b
+#define PCI_DEVICE_ID_INTEL_CFL_S_GT2			0x3e92
 
 /* Intel Northbridge Ids */
 #define PCI_DEVICE_ID_INTEL_APL_NB	0x5af0
@@ -2908,12 +2945,15 @@
 #define PCI_DEVICE_ID_INTEL_WHL_ID_Wx4	0x3E34
 #define PCI_DEVICE_ID_INTEL_WHL_ID_Wx2	0x3E35
 #define PCI_DEVICE_ID_INTEL_CFL_ID_U	0x3ED0
+#define PCI_DEVICE_ID_INTEL_CFL_ID_H	0x3ec4
+#define PCI_DEVICE_ID_INTEL_CFL_ID_S	0x3ec2
 
 /* Intel SMBUS device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS		0x9d23
 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS			0xa123
 #define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS			0xa1a3
 #define PCI_DEVICE_ID_INTEL_CNL_SMBUS			0x9da3
+#define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS			0xa323
 
 /* Intel XHCI device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_XHCI		0x5aa8
@@ -2922,16 +2962,19 @@
 #define PCI_DEVICE_ID_INTEL_SPT_H_XHCI		0xa12f
 #define PCI_DEVICE_ID_INTEL_KBP_H_XHCI		0xa2af
 #define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI		0x9ded
+#define PCI_DEVICE_ID_INTEL_CNP_H_XHCI		0xa36d
 
 /* Intel P2SB device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_P2SB		0x5a92
 #define PCI_DEVICE_ID_INTEL_GLK_P2SB		0x3192
 #define PCI_DEVICE_ID_INTEL_CNL_P2SB		0x9da0
+#define PCI_DEVICE_ID_INTEL_CNP_H_P2SB		0xa320
 
 /* Intel SRAM device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_SRAM		0x5aec
 #define PCI_DEVICE_ID_INTEL_GLK_SRAM		0x31ec
 #define PCI_DEVICE_ID_INTEL_CNL_SRAM		0x9def
+#define PCI_DEVICE_ID_INTEL_CNP_H_SRAM		0xa36f
 
 /* Intel AUDIO device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_AUDIO		0x5a98
@@ -2939,24 +2982,28 @@
 #define PCI_DEVICE_ID_INTEL_CNL_AUDIO		0x9dc8
 #define PCI_DEVICE_ID_INTEL_SKL_AUDIO		0x9d70
 #define PCI_DEVICE_ID_INTEL_KBL_AUDIO		0x9d71
+#define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO		0xa348
 
 /* Intel HECI/ME device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_CSE0		0x5a9a
 #define PCI_DEVICE_ID_INTEL_GLK_CSE0		0x319a
 #define PCI_DEVICE_ID_INTEL_CNL_CSE0		0x9de0
 #define PCI_DEVICE_ID_INTEL_SKL_CSE0		0x9d3a
+#define PCI_DEVICE_ID_INTEL_CNP_H_CSE0		0xa360
 
 /* Intel XDCI device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_XDCI		0x5aaa
 #define PCI_DEVICE_ID_INTEL_GLK_XDCI		0x31aa
 #define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI		0x9d30
 #define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI		0x9dee
+#define PCI_DEVICE_ID_INTEL_CNP_H_XDCI		0xa36e
 
 /* Intel SD device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_SD		0x5aca
 #define PCI_DEVICE_ID_INTEL_GLK_SD		0x31ca
 #define PCI_DEVICE_ID_INTEL_SKL_SD		0x9d2d
 #define PCI_DEVICE_ID_INTEL_CNL_SD		0x9df5
+#define PCI_DEVICE_ID_INTEL_CNP_H_SD		0xa375
 
 /* Intel EMMC device Ids */
 #define PCI_DEVICE_ID_INTEL_SKL_EMMC		0x9d2b
@@ -2969,6 +3016,8 @@
 #define PCH_CNL_LP_U_PREMIUM			0x9d84
 #define PCH_CNL_LP_U_BASE			0x9d85
 #define PCH_CNL_H_DT_SUPER			0xa280
+#define PCH_CNP_H_MOBILE_Q370			0xa306
+#define PCH_CNP_H_MOBILE_QM370			0xa30c
 
 /* Intel WIFI Ids */
 #define PCI_DEVICE_ID_1000_SERIES_WIFI		0x0084

src/soc/intel/cannonlake/Kconfig

@@ -204,6 +204,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 
 config SOC_INTEL_I2C_DEV_MAX
 	int
+	default 4 if CANNONLAKE_SOC_PCH_H
 	default 6
 
 # Clock divider parameters for 115200 baud rate

src/soc/intel/cannonlake/bootblock/report_platform.c

@@ -38,6 +38,7 @@ static struct {
 	{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
 	{ CPUID_COFFEELAKE_D0, "Coffeelake D0" },
 	{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},
+	{ CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" },
 };
 
 static struct {
@@ -49,6 +50,8 @@ static struct {
 	{ PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"},
 	{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)"},
 	{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)"},
+	{ PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" },
+	{ PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" },
 };
 
 static struct {
@@ -58,6 +61,8 @@ static struct {
 	{ PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
 	{ PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
 	{ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
+	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" },
+	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" },
 };
 
 static struct {
@@ -74,6 +79,8 @@ static struct {
 	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
 	{ PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"},
 	{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"},
+	{ PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" },
+	{ PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" },
 };
 
 static uint8_t get_dev_revision(pci_devfn_t dev)

src/soc/intel/cannonlake/chip.c

@@ -75,6 +75,14 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_PCIE14:	return "RP14";
 	case PCH_DEVFN_PCIE15:	return "RP15";
 	case PCH_DEVFN_PCIE16:	return "RP16";
+	case PCH_DEVFN_PCIE17:	return "RP17";
+	case PCH_DEVFN_PCIE18:	return "RP18";
+	case PCH_DEVFN_PCIE19:	return "RP19";
+	case PCH_DEVFN_PCIE20:	return "RP20";
+	case PCH_DEVFN_PCIE21:	return "RP21";
+	case PCH_DEVFN_PCIE22:	return "RP22";
+	case PCH_DEVFN_PCIE23:	return "RP23";
+	case PCH_DEVFN_PCIE24:	return "RP24";
 	case PCH_DEVFN_UART0:	return "UAR0";
 	case PCH_DEVFN_UART1:	return "UAR1";
 	case PCH_DEVFN_GSPI0:	return "SPI0";

src/soc/intel/cannonlake/include/soc/pci_devs.h

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -147,6 +147,24 @@
 #define  PCH_DEV_PCIE15		_PCH_DEV(PCIE_1, 6)
 #define  PCH_DEV_PCIE16		_PCH_DEV(PCIE_1, 7)
 
+#define PCH_DEV_SLOT_PCIE_2	0x1b
+#define  PCH_DEVFN_PCIE17	_PCH_DEVFN(PCIE_2, 0)
+#define  PCH_DEVFN_PCIE18	_PCH_DEVFN(PCIE_2, 1)
+#define  PCH_DEVFN_PCIE19	_PCH_DEVFN(PCIE_2, 2)
+#define  PCH_DEVFN_PCIE20	_PCH_DEVFN(PCIE_2, 3)
+#define  PCH_DEVFN_PCIE21	_PCH_DEVFN(PCIE_2, 4)
+#define  PCH_DEVFN_PCIE22	_PCH_DEVFN(PCIE_2, 5)
+#define  PCH_DEVFN_PCIE23	_PCH_DEVFN(PCIE_2, 6)
+#define  PCH_DEVFN_PCIE24	_PCH_DEVFN(PCIE_2, 7)
+#define  PCH_DEV_PCIE17		_PCH_DEV(PCIE_2, 0)
+#define  PCH_DEV_PCIE18		_PCH_DEV(PCIE_2, 1)
+#define  PCH_DEV_PCIE19		_PCH_DEV(PCIE_2, 2)
+#define  PCH_DEV_PCIE20		_PCH_DEV(PCIE_2, 3)
+#define  PCH_DEV_PCIE21		_PCH_DEV(PCIE_2, 4)
+#define  PCH_DEV_PCIE22		_PCH_DEV(PCIE_2, 5)
+#define  PCH_DEV_PCIE23		_PCH_DEV(PCIE_2, 6)
+#define  PCH_DEV_PCIE24		_PCH_DEV(PCIE_2, 7)
+
 #define PCH_DEV_SLOT_SIO3	0x1e
 #define  PCH_DEVFN_UART0	_PCH_DEVFN(SIO3, 0)
 #define  PCH_DEVFN_UART1	_PCH_DEVFN(SIO3, 1)

src/soc/intel/cannonlake/romstage/fsp_params.c

@@ -31,7 +31,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
 	m_cfg->SaGv = config->SaGv;
-	m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+	if (IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H))
+		m_cfg->UserBd = BOARD_TYPE_DESKTOP;
+	else
+		m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
 	m_cfg->RMT = config->RMT;
 
 	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {

src/soc/intel/common/block/cse/cse.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2017 Intel Inc.
+ * Copyright 2017-2018 Intel Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -518,6 +518,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_CSE0,
 	PCI_DEVICE_ID_INTEL_CNL_CSE0,
 	PCI_DEVICE_ID_INTEL_SKL_CSE0,
+	PCI_DEVICE_ID_INTEL_CNP_H_CSE0,
 	0,
 };
 

src/soc/intel/common/block/dsp/dsp.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  *  * Copyright (C) 2016 Google Inc.
- *  * Copyright (C) 2017 Intel Corporation.
+ *  * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -31,6 +31,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_AUDIO,
 	PCI_DEVICE_ID_INTEL_GLK_AUDIO,
 	PCI_DEVICE_ID_INTEL_SKL_AUDIO,
+	PCI_DEVICE_ID_INTEL_CNP_H_AUDIO,
 	0,
 };
 

src/soc/intel/common/block/graphics/graphics.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -132,6 +132,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,
 	PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,
 	PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
+	PCI_DEVICE_ID_INTEL_CFL_H_GT2,
+	PCI_DEVICE_ID_INTEL_CFL_S_GT2,
 	0,
 };
 

src/soc/intel/common/block/i2c/i2c.c

@@ -213,6 +213,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_I2C5,
 	PCI_DEVICE_ID_INTEL_GLK_I2C6,
 	PCI_DEVICE_ID_INTEL_GLK_I2C7,
+	PCI_DEVICE_ID_INTEL_CNP_H_I2C0,
+	PCI_DEVICE_ID_INTEL_CNP_H_I2C1,
+	PCI_DEVICE_ID_INTEL_CNP_H_I2C2,
+	PCI_DEVICE_ID_INTEL_CNP_H_I2C3,
 	0,
 };
 

src/soc/intel/common/block/lpc/lpc.c

@@ -144,6 +144,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,
 	PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,
 	PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
+	PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370,
+	PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370,
 	0
 };
 

src/soc/intel/common/block/p2sb/p2sb.c

@@ -166,6 +166,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_APL_P2SB,
 	PCI_DEVICE_ID_INTEL_GLK_P2SB,
 	PCI_DEVICE_ID_INTEL_CNL_P2SB,
+	PCI_DEVICE_ID_INTEL_CNP_H_P2SB,
 	0,
 };
 

src/soc/intel/common/block/pcie/pcie.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -166,6 +166,30 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14,
 	PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15,
 	PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23,
+	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24,
 	0
 };
 

src/soc/intel/common/block/pmc/pmc.c

@@ -126,6 +126,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_KBP_H_PMC,
 	PCI_DEVICE_ID_INTEL_APL_PMC,
 	PCI_DEVICE_ID_INTEL_GLK_PMC,
+	PCI_DEVICE_ID_INTEL_CNP_H_PMC,
 	0
 };
 

src/soc/intel/common/block/scs/sd.c

@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright 2017 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -69,6 +70,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_SD,
 	PCI_DEVICE_ID_INTEL_GLK_SD,
 	PCI_DEVICE_ID_INTEL_SKL_SD,
+	PCI_DEVICE_ID_INTEL_CNP_H_SD,
 	0
 };
 

src/soc/intel/common/block/systemagent/systemagent.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -304,6 +304,8 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DEVICE_ID_INTEL_KBL_U_R,
 	PCI_DEVICE_ID_INTEL_KBL_ID_DT,
 	PCI_DEVICE_ID_INTEL_CFL_ID_U,
+	PCI_DEVICE_ID_INTEL_CFL_ID_H,
+	PCI_DEVICE_ID_INTEL_CFL_ID_S,
 	0
 };
 

src/soc/intel/common/block/uart/uart.c

@@ -262,6 +262,9 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_UART1,
 	PCI_DEVICE_ID_INTEL_GLK_UART2,
 	PCI_DEVICE_ID_INTEL_GLK_UART3,
+	PCI_DEVICE_ID_INTEL_CNP_H_UART0,
+	PCI_DEVICE_ID_INTEL_CNP_H_UART1,
+	PCI_DEVICE_ID_INTEL_CNP_H_UART2,
 	0,
 };
 

src/soc/intel/common/block/xdci/xdci.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2017 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -41,6 +41,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_LP_XDCI,
 	PCI_DEVICE_ID_INTEL_GLK_XDCI,
 	PCI_DEVICE_ID_INTEL_SPT_LP_XDCI,
+	PCI_DEVICE_ID_INTEL_CNP_H_XDCI,
 	0
 };
 

src/soc/intel/common/block/xhci/xhci.c

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -42,6 +42,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_SPT_LP_XHCI,
 	PCI_DEVICE_ID_INTEL_SPT_H_XHCI,
 	PCI_DEVICE_ID_INTEL_KBP_H_XHCI,
+	PCI_DEVICE_ID_INTEL_CNP_H_XHCI,
 	0
 };