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nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK 

Console init in bootblock will be done in a separate CL.

Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-11-12 23:34:13 +01:00 committed by Patrick Georgi
parent dc584c3f22
commit e27c013f39
13 changed files with 38 additions and 77 deletions
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4
src/cpu/intel/car/core2/cache_as_ram.S
View File

@ -18,14 +18,10 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif
.global bootblock_pre_c_entry

8
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@ -18,22 +18,14 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/* Fixed location, ASSERTED in failover.ld if it changes. */
.set ap_sipi_vector_in_rom, 0xff
#endif
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif
.global bootblock_pre_c_entry

9
src/cpu/intel/socket_441/Kconfig
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@ -8,6 +8,11 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_106CX
select MMX
select SSE
select SETUP_XIP_CACHE
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x4000
config DCACHE_RAM_BASE
hex
@ -17,4 +22,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
endif # CPU_INTEL_SOCKET_441

3
src/cpu/intel/socket_441/Makefile.inc
View File

@ -8,7 +8,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
bootblock-y += ../car/p4-netburst/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c

8
src/cpu/intel/socket_m/Kconfig
View File

@ -18,4 +18,12 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x8000
endif

3
src/cpu/intel/socket_m/Makefile.inc
View File

@ -9,7 +9,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
bootblock-y += ../car/core2/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c

6
src/northbridge/intel/i945/Kconfig
View File

@ -27,16 +27,14 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_EDID
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select PARALLEL_MP
select C_ENVIRONMENT_BOOTBLOCK
select NO_BOOTBLOCK_CONSOLE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
def_bool n
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/i945/bootblock.c"
config VGA_BIOS_ID
string
default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM

2
src/northbridge/intel/i945/Makefile.inc
View File

@ -15,6 +15,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y)
bootblock-y += bootblock.c
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += gma.c

7
src/northbridge/intel/i945/bootblock.c
View File

@ -11,12 +11,11 @@
* GNU General Public License for more details.
*/
#include <cpu/intel/car/bootblock.h>
#include <device/pci_ops.h>
#include "i945.h"
/* Just re-define this instead of including i945.h. It blows up romcc. */
#define PCIEXBAR 0x48
static void bootblock_northbridge_init(void)
void bootblock_early_northbridge_init(void)
{
uint32_t reg;

4
src/southbridge/intel/i82801gx/Kconfig
View File

@ -40,10 +40,6 @@ config EHCI_BAR
hex
default 0xfef00000
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801gx/bootblock.c"
config HPET_MIN_TICKS
hex
default 0x80

2
src/southbridge/intel/i82801gx/Makefile.inc
View File

@ -16,7 +16,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
bootblock-y += early_init.c
bootblock-y += bootblock_gcc.c
bootblock-y += bootblock.c
ramstage-y += i82801gx.c
ramstage-y += ac97.c

15
src/southbridge/intel/i82801gx/bootblock.c
View File

@ -14,14 +14,13 @@
*/
#include <device/pci_ops.h>
#include <cpu/intel/car/bootblock.h>
#include "i82801gx.h"
static void enable_spi_prefetch(void)
{
u8 reg8;
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(3 << 2);
@ -29,13 +28,17 @@ static void enable_spi_prefetch(void)
pci_write_config8(dev, BIOS_CNTL, reg8);
}
static void bootblock_southbridge_init(void)
void bootblock_early_southbridge_init(void)
{
enable_spi_prefetch();
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
i82801gx_setup_bars();
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
/* Disable watchdog timer */
RCBA32(GCS) = RCBA32(GCS) | 0x20;
i82801gx_lpc_setup();
}

44
src/southbridge/intel/i82801gx/bootblock_gcc.c
View File

@ -1,44 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ops.h>
#include <cpu/intel/car/bootblock.h>
#include "i82801gx.h"
static void enable_spi_prefetch(void)
{
u8 reg8;
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_write_config8(dev, BIOS_CNTL, reg8);
}
void bootblock_early_southbridge_init(void)
{
enable_spi_prefetch();
i82801gx_setup_bars();
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
/* Disable watchdog timer */
RCBA32(GCS) = RCBA32(GCS) | 0x20;
i82801gx_lpc_setup();
}