siemens/mc_apl1: Correct the Tx signal from SATA interface

Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3.

Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>

src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c

@@ -27,6 +27,8 @@
 #include <baseboard/variants.h>
 #include <variant/ptn3460.h>
 
+#define TX_DWORD3	0xa8c
+
 void variant_mainboard_final(void)
 {
 	int status;
@@ -63,6 +65,14 @@ void variant_mainboard_final(void)
 	 * offset 0x341C bit [3:0].
 	 */
 	pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
+
+	/*
+	 * Correct the SATA transmit signal via the High Speed I/O Transmit
+	 * Control Register 3.
+	 * Bit [23:16] set the output voltage swing for TX line.
+	 * The value 0x4a sets the swing level to 0.58 V.
+	 */
+	pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
 }
 
 static void wait_for_legacy_dev(void *unused)

src/soc/intel/apollolake/include/soc/pcr_ids.h

@@ -33,6 +33,7 @@
 #define PID_ITSS	0xD0
 #define PID_RTC		0xD1
 #define PID_LPC		0xD2
+#define PID_MODPHY	0xA5
 
 #define PID_AUNIT	0x4d
 #define PID_BUNIT	0x4c