timestamps intel: Move timestamp scratchpad to chipset

This retrieves back the value stored with store_initial_timestamp()
in the bootblock for southbridge.

Change-Id: I377c823706c33ed65af023d20d2e4323edd31199
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/cpu/intel/haswell/romstage.c

@@ -204,10 +204,7 @@ void romstage_common(const struct romstage_params *params)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 
 #if CONFIG_COLLECT_TIMESTAMPS

src/include/timestamp.h

@@ -61,6 +61,7 @@ void timestamp_add(enum timestamp_id id, tsc_t ts_time);
 void timestamp_add_now(enum timestamp_id id);
 void timestamp_stash(enum timestamp_id id);
 void timestamp_sync(void);
+tsc_t get_initial_timestamp(void);
 #else
 #define timestamp_init(base)
 #define timestamp_add(id, time)

src/mainboard/google/butterfly/romstage.c

@@ -122,10 +122,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,

src/mainboard/google/link/romstage.c

@@ -158,10 +158,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,

src/mainboard/google/parrot/romstage.c

@@ -123,10 +123,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,

src/mainboard/google/stout/romstage.c

@@ -162,10 +162,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,

src/mainboard/intel/emeraldlake2/romstage.c

@@ -174,10 +174,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,

src/mainboard/kontron/ktqm77/romstage.c

@@ -160,10 +160,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,

src/mainboard/lenovo/t60/romstage.c

@@ -216,10 +216,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 
 #if CONFIG_COLLECT_TIMESTAMPS

src/mainboard/lenovo/x60/romstage.c

@@ -223,10 +223,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 
 #if CONFIG_COLLECT_TIMESTAMPS

src/mainboard/samsung/lumpy/romstage.c

@@ -141,10 +141,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,

src/mainboard/samsung/stumpy/romstage.c

@@ -177,10 +177,7 @@ void main(unsigned long bist)
 	tsc_t start_romstage_time;
 	tsc_t before_dram_time;
 	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
+	tsc_t base_time = get_initial_timestamp();
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,

src/southbridge/intel/bd82x6x/Makefile.inc

@@ -47,7 +47,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
 
 romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
 romstage-y += reset.c
-romstage-y += early_spi.c
+romstage-y += early_spi.c early_pch.c
 
 ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 IFD_BIN_PATH := $(objgenerated)/ifdfake.bin

src/southbridge/intel/bd82x6x/early_pch.c

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <timestamp.h>
+
+#if CONFIG_COLLECT_TIMESTAMPS
+tsc_t get_initial_timestamp(void)
+{
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+	return base_time;
+}
+#endif

src/southbridge/intel/i82801gx/Makefile.inc

@@ -36,5 +36,4 @@ ramstage-y += watchdog.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
-romstage-y += early_smbus.c
-
+romstage-y += early_smbus.c early_lpc.c

src/southbridge/intel/i82801gx/early_lpc.c

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <timestamp.h>
+
+#if CONFIG_COLLECT_TIMESTAMPS
+tsc_t get_initial_timestamp(void)
+{
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+	return base_time;
+}
+#endif

src/southbridge/intel/lynxpoint/early_pch.c

@@ -21,6 +21,7 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
+#include <timestamp.h>
 #include <elog.h>
 #include "pch.h"
 
@@ -62,6 +63,17 @@ static void pch_generic_setup(void)
 	printk(BIOS_DEBUG, " done.\n");
 }
 
+#if CONFIG_COLLECT_TIMESTAMPS
+tsc_t get_initial_timestamp(void)
+{
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+	return base_time;
+}
+#endif
+
 static int sleep_type_s3(void)
 {
 	u32 pm1_cnt;