GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntax 

It builds same binary for apple/macbook21 using BUILD_TIMELESS=1

Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45272
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-09-10 20:36:14 +02:00 committed by Patrick Georgi
parent 08b5ef4834
commit e298391337
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/northbridge/intel/i945/acpi/i945.asl
View File

@ -8,13 +8,13 @@
Method (_OSC, 4) Method (_OSC, 4)
{ {
/* Check for proper PCI/PCIe UUID */ /* Check for proper PCI/PCIe UUID */
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
{ {
/* Let OS control everything */ /* Let OS control everything */
Return(Arg3) Return(Arg3)
} Else { } Else {
CreateDWordField(Arg3, 0, CDW1) CreateDWordField(Arg3, 0, CDW1)
Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 CDW1 = CDW1 | 4 // Unrecognized UUID, so set bit 2 to 1
Return(Arg3) Return(Arg3)
} }
} }
@ -52,22 +52,22 @@ Device (PDRC)
Method (_CRS, 0, Serialized) Method (_CRS, 0, Serialized)
{ {
//CreateDwordField(PDRS, ^RCRB._BAS, RBR0) //CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
//ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) //RBR0 = \_SB.PCI0.LPCB.RCBA << 14
//CreateDwordField(PDRS, ^MCHB._BAS, MBR0) //CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
//ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) //MBR0 = \_SB.PCI0.MCHC.MHBR << 14
//CreateDwordField(PDRS, ^DMIB._BAS, DBR0) //CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
//ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) //DBR0 = \_SB.PCI0.MCHC.DMBR << 12
//CreateDwordField(PDRS, ^EGPB._BAS, EBR0) //CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
//ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) //EBR0 = \_SB.PCI0.MCHC.EPBR << 12
//CreateDwordField(PDRS, ^PCIE._BAS, PBR0) //CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
//ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) //PBR0 = \_SB.PCI0.MCHC.PXBR << 26
//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
//ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) //PSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ
Return(PDRS) Return(PDRS)
} }