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Fix up and document the AMD CS5530/CS5530A support in flashrom. 

The previous code was pretty unreadable, undocumented and did some totally
unrelated things (such as mucking with the game port or port 0x92).

This version is tested with a 256 KB chip and should work for the
CS5530 and CS5530A.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2007-06-06 21:35:45 +00:00
parent ecbe8e5d5c
commit e29a664b54
2 changed files with 22 additions and 11 deletions
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2
util/flashrom/README
View File

@ -150,7 +150,7 @@ Winbond W39V080A
Supported Southbridges Supported Southbridges
---------------------- ----------------------
AMD CS5530 AMD CS5530/CS5530A
AMD Geode SC1100 AMD Geode SC1100
AMD AMD-8111 AMD AMD-8111
ATI SB400 ATI SB400

31
util/flashrom/chipset_enable.c
View File

@ -183,19 +183,30 @@ static int enable_flash_vt823x(struct pci_dev *dev, char *name)
static int enable_flash_cs5530(struct pci_dev *dev, char *name) static int enable_flash_cs5530(struct pci_dev *dev, char *name)
{ {
uint8_t new; uint8_t reg8;
pci_write_byte(dev, 0x52, 0xee); #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
new = pci_read_byte(dev, 0x52); #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
#define ROM_WRITE_ENABLE (1 << 1)
#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
if (new != 0xee) { /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
return -1; * Make the configured ROM areas writable.
} */
reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
reg8 |= LOWER_ROM_ADDRESS_RANGE;
reg8 |= UPPER_ROM_ADDRESS_RANGE;
reg8 |= ROM_WRITE_ENABLE;
pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
new = pci_read_byte(dev, 0x5b) | 0x20; /* Set positive decode on ROM. */
pci_write_byte(dev, 0x5b, new); reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
reg8 |= BIOS_ROM_POSITIVE_DECODE;
pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
return 0; return 0;
} }
@ -435,7 +446,7 @@ static FLASH_ENABLE enables[] = {
{0x1106, 0x3227, "VT8237", enable_flash_vt823x}, {0x1106, 0x3227, "VT8237", enable_flash_vt823x},
{0x1106, 0x8324, "CX700", enable_flash_vt823x}, {0x1106, 0x8324, "CX700", enable_flash_vt823x},
{0x1106, 0x0686, "VT82C686", enable_flash_amd8111}, {0x1106, 0x0686, "VT82C686", enable_flash_amd8111},
{0x1078, 0x0100, "CS5530", enable_flash_cs5530}, {0x1078, 0x0100, "CS5530/CS5530A", enable_flash_cs5530},
{0x100b, 0x0510, "SC1100", enable_flash_sc1100}, {0x100b, 0x0510, "SC1100", enable_flash_sc1100},
{0x1039, 0x0008, "SIS5595", enable_flash_sis5595}, {0x1039, 0x0008, "SIS5595", enable_flash_sis5595},
{0x1022, 0x7468, "AMD8111", enable_flash_amd8111}, {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},