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intel/fsp: Update cannonlake fsp header 

Update Cannonlake FSP header to revision 7.x.20.52. Following changes
had been made:
1. Hide internal EV related options.
2. Add GT voltage override options.
3. Add PEG IMR selection.
4. Add PCH DMI ASPM options.

TEST=NONE

Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Lijian Zhao 2018-01-21 22:37:21 -08:00 committed by Subrata Banik
parent b2e1109f0f
commit e2a7bf16f0
3 changed files with 388 additions and 194 deletions
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2
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspUpd.h
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@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:

414
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
View File

@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
@ -282,9 +282,10 @@ typedef struct {
UINT8 UnusedUpdSpace1; UINT8 UnusedUpdSpace1;
/** Offset 0x00BE - DDR Frequency Limit /** Offset 0x00BE - DDR Frequency Limit
Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
2133, 2400, 2667, 2933 and 0 for Auto. i.e. divide by 133 or 100
1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133,
2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto
**/ **/
UINT16 DdrFreqLimit; UINT16 DdrFreqLimit;
@ -326,25 +327,9 @@ typedef struct {
**/ **/
UINT8 ScramblerSupport; UINT8 ScramblerSupport;
/** Offset 0x00C8 - EV Loader Test Content Pointer /** Offset 0x00C8
Pointer to EV Loader Test Content in Memory
**/ **/
UINT32 EvTestContentPtr; UINT8 UnusedUpdSpace2[16];
/** Offset 0x00CC - EV Loader Test Content Size
Size of EV Loader Test Content in Memory
**/
UINT32 EvTestContentSize;
/** Offset 0x00D0 - EV Loader Test Config Pointer
Pointer to EV Loader Test Config in Memory
**/
UINT32 EvTestConfigPtr;
/** Offset 0x00D4 - EV Loader Test Config Size
Size of EV Loader Test Config in Memory
**/
UINT32 EvTestConfigSize;
/** Offset 0x00D8 - SPD Profile Selected /** Offset 0x00D8 - SPD Profile Selected
Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
@ -491,7 +476,7 @@ typedef struct {
/** Offset 0x00F6 /** Offset 0x00F6
**/ **/
UINT8 UnusedUpdSpace2[6]; UINT8 UnusedUpdSpace3[6];
/** Offset 0x00FC - Enable Intel HD Audio (Azalia) /** Offset 0x00FC - Enable Intel HD Audio (Azalia)
0: Disable, 1: Enable (Default) Azalia controller 0: Disable, 1: Enable (Default) Azalia controller
@ -513,7 +498,7 @@ typedef struct {
/** Offset 0x00FF /** Offset 0x00FF
**/ **/
UINT8 UnusedUpdSpace3; UINT8 UnusedUpdSpace4;
/** Offset 0x0100 - HECI1 BAR address /** Offset 0x0100 - HECI1 BAR address
BAR address of HECI1 BAR address of HECI1
@ -684,7 +669,7 @@ typedef struct {
/** Offset 0x0125 /** Offset 0x0125
**/ **/
UINT8 UnusedUpdSpace4[3]; UINT8 UnusedUpdSpace5[3];
/** Offset 0x0128 - DMI Gen3 Root port preset values per lane /** Offset 0x0128 - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
@ -708,7 +693,7 @@ typedef struct {
/** Offset 0x0144 /** Offset 0x0144
**/ **/
UINT8 UnusedUpdSpace5[4]; UINT8 UnusedUpdSpace6[4];
/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
Range: 0-15, 12 is default for each bundle, must be specified based upon platform design Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
@ -867,11 +852,37 @@ typedef struct {
**/ **/
UINT8 GtPsmiSupport; UINT8 GtPsmiSupport;
/** Offset 0x01F4 - SaPreMemProductionRsvd /** Offset 0x01F4 - GT unslice Voltage Mode
0(Default): Adaptive, 1: Override
0: Adaptive, 1: Override
**/
UINT8 GtusVoltageMode;
/** Offset 0x01F5 - voltage offset applied to GT unslice
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtusVoltageOffset;
/** Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtusVoltageOverride;
/** Offset 0x01F9 - adaptive voltage applied during turbo frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtusExtraTurboVoltage;
/** Offset 0x01FB - Maximum GTus turbo ratio override
0(Default)=Minimal, 60=Maximum
**/
UINT8 GtusMaxOcRatio;
/** Offset 0x01FC - SaPreMemProductionRsvd
Reserved for SA Pre-Mem Production Reserved for SA Pre-Mem Production
$EN_DIS $EN_DIS
**/ **/
UINT8 SaPreMemProductionRsvd[12]; UINT8 SaPreMemProductionRsvd[4];
/** Offset 0x0200 - BIST on Reset /** Offset 0x0200 - BIST on Reset
Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable. Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
@ -919,7 +930,7 @@ typedef struct {
/** Offset 0x0207 /** Offset 0x0207
**/ **/
UINT8 UnusedUpdSpace6; UINT8 UnusedUpdSpace7;
/** Offset 0x0208 - Maximum clr turbo ratio override /** Offset 0x0208 - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
@ -1016,7 +1027,7 @@ typedef struct {
/** Offset 0x021A - Ring Downbin /** Offset 0x021A - Ring Downbin
Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
lower than the core ratio.<b>0: Disable</b>; 1: Enable. lower than the core ratio.0: Disable; <b>1: Enable.</b>
$EN_DIS $EN_DIS
**/ **/
UINT8 RingDownBin; UINT8 RingDownBin;
@ -1074,7 +1085,7 @@ typedef struct {
/** Offset 0x0227 /** Offset 0x0227
**/ **/
UINT8 UnusedUpdSpace7; UINT8 UnusedUpdSpace8;
/** Offset 0x0228 - PrmrrSize /** Offset 0x0228 - PrmrrSize
0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
@ -1669,12 +1680,12 @@ typedef struct {
UINT8 EnableOltm; UINT8 EnableOltm;
/** Offset 0x04A2 - DDR PowerDown and idle counter /** Offset 0x04A2 - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) Enables/Disable DDR PowerDown and idle counter
$EN_DIS $EN_DIS
**/ **/
UINT8 EnablePwrDn; UINT8 EnablePwrDn;
/** Offset 0x04A3 - DDR PowerDown and idle counter /** Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS $EN_DIS
**/ **/
@ -1711,7 +1722,7 @@ typedef struct {
**/ **/
UINT8 SrefCfgEna; UINT8 SrefCfgEna;
/** Offset 0x04A9 - Throttler CKEMin Defeature /** Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR
Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
$EN_DIS $EN_DIS
**/ **/
@ -1741,431 +1752,415 @@ typedef struct {
**/ **/
UINT8 DdrThermalSensor; UINT8 DdrThermalSensor;
/** Offset 0x04AE - EV Loader /** Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
Enable/Disable EV Loader Functionality
$EN_DIS
**/
UINT8 EvLoader;
/** Offset 0x04AF - EV Loader Delay
Enable/Disable EV Loader 2 Second Delay
$EN_DIS
**/
UINT8 EvLoaderDelay;
/** Offset 0x04B0 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
$EN_DIS $EN_DIS
**/ **/
UINT8 Ddr4DdpSharedClock; UINT8 Ddr4DdpSharedClock;
/** Offset 0x04B1 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP /** Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
$EN_DIS $EN_DIS
**/ **/
UINT8 Ddr4DdpSharedZq; UINT8 Ddr4DdpSharedZq;
/** Offset 0x04B2 - Ch Hash Mask /** Offset 0x04B0 - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
BITS [19:6 BITS [19:6
**/ **/
UINT16 ChHashMask; UINT16 ChHashMask;
/** Offset 0x04B4 - Base reference clock value /** Offset 0x04B2 - Base reference clock value
Base reference clock value, in Hertz(Default is 125Hz) Base reference clock value, in Hertz(Default is 125Hz)
100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
**/ **/
UINT32 BClkFrequency; UINT32 BClkFrequency;
/** Offset 0x04B8 - Ch Hash Interleaved Bit /** Offset 0x04B6 - Ch Hash Interleaved Bit
Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
**/ **/
UINT8 ChHashInterleaveBit; UINT8 ChHashInterleaveBit;
/** Offset 0x04B9 - Energy Scale Factor /** Offset 0x04B7 - Energy Scale Factor
Energy Scale Factor, Default is 4 Energy Scale Factor, Default is 4
**/ **/
UINT8 EnergyScaleFact; UINT8 EnergyScaleFact;
/** Offset 0x04BA - EPG DIMM Idd3N /** Offset 0x04B8 - EPG DIMM Idd3N
Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
a per DIMM basis. Default is 26 a per DIMM basis. Default is 26
**/ **/
UINT16 Idd3n; UINT16 Idd3n;
/** Offset 0x04BC - EPG DIMM Idd3P /** Offset 0x04BA - EPG DIMM Idd3P
Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
on a per DIMM basis. Default is 11 on a per DIMM basis. Default is 11
**/ **/
UINT16 Idd3p; UINT16 Idd3p;
/** Offset 0x04BE - CMD Slew Rate Training /** Offset 0x04BC - CMD Slew Rate Training
Enable/Disable CMD Slew Rate Training Enable/Disable CMD Slew Rate Training
$EN_DIS $EN_DIS
**/ **/
UINT8 CMDSR; UINT8 CMDSR;
/** Offset 0x04BF - CMD Drive Strength and Tx Equalization /** Offset 0x04BD - CMD Drive Strength and Tx Equalization
Enable/Disable CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equalization
$EN_DIS $EN_DIS
**/ **/
UINT8 CMDDSEQ; UINT8 CMDDSEQ;
/** Offset 0x04C0 - CMD Normalization /** Offset 0x04BE - CMD Normalization
Enable/Disable CMD Normalization Enable/Disable CMD Normalization
$EN_DIS $EN_DIS
**/ **/
UINT8 CMDNORM; UINT8 CMDNORM;
/** Offset 0x04C1 - Early DQ Write Drive Strength and Equalization Training /** Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training
Enable/Disable Early DQ Write Drive Strength and Equalization Training Enable/Disable Early DQ Write Drive Strength and Equalization Training
$EN_DIS $EN_DIS
**/ **/
UINT8 EWRDSEQ; UINT8 EWRDSEQ;
/** Offset 0x04C2 - RH Activation Probability /** Offset 0x04C0 - RH Activation Probability
RH Activation Probability, Probability value is 1/2^(inputvalue) RH Activation Probability, Probability value is 1/2^(inputvalue)
**/ **/
UINT8 RhActProbability; UINT8 RhActProbability;
/** Offset 0x04C3 - RAPL PL 2 WindowX /** Offset 0x04C1 - RAPL PL 2 WindowX
Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
**/ **/
UINT8 RaplLim2WindX; UINT8 RaplLim2WindX;
/** Offset 0x04C4 - RAPL PL 2 WindowY /** Offset 0x04C2 - RAPL PL 2 WindowY
Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
**/ **/
UINT8 RaplLim2WindY; UINT8 RaplLim2WindY;
/** Offset 0x04C5 - RAPL PL 1 WindowX /** Offset 0x04C3 - RAPL PL 1 WindowX
Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
**/ **/
UINT8 RaplLim1WindX; UINT8 RaplLim1WindX;
/** Offset 0x04C6 - RAPL PL 1 WindowY /** Offset 0x04C4 - RAPL PL 1 WindowY
Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
**/ **/
UINT8 RaplLim1WindY; UINT8 RaplLim1WindY;
/** Offset 0x04C7 /** Offset 0x04C5 - RAPL PL 2 Power
**/
UINT8 UnusedUpdSpace8;
/** Offset 0x04C8 - RAPL PL 2 Power
range[0;2^14-1]= [2047.875;0]in W, (224= Def) range[0;2^14-1]= [2047.875;0]in W, (224= Def)
**/ **/
UINT16 RaplLim2Pwr; UINT16 RaplLim2Pwr;
/** Offset 0x04CA - RAPL PL 1 Power /** Offset 0x04C7 - RAPL PL 1 Power
range[0;2^14-1]= [2047.875;0]in W, (224= Def) range[0;2^14-1]= [2047.875;0]in W, (224= Def)
**/ **/
UINT16 RaplLim1Pwr; UINT16 RaplLim1Pwr;
/** Offset 0x04CC - Warm Threshold Ch0 Dimm0 /** Offset 0x04C9 - Warm Threshold Ch0 Dimm0
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
**/ **/
UINT8 WarmThresholdCh0Dimm0; UINT8 WarmThresholdCh0Dimm0;
/** Offset 0x04CD - Warm Threshold Ch0 Dimm1 /** Offset 0x04CA - Warm Threshold Ch0 Dimm1
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
**/ **/
UINT8 WarmThresholdCh0Dimm1; UINT8 WarmThresholdCh0Dimm1;
/** Offset 0x04CE - Warm Threshold Ch1 Dimm0 /** Offset 0x04CB - Warm Threshold Ch1 Dimm0
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
**/ **/
UINT8 WarmThresholdCh1Dimm0; UINT8 WarmThresholdCh1Dimm0;
/** Offset 0x04CF - Warm Threshold Ch1 Dimm1 /** Offset 0x04CC - Warm Threshold Ch1 Dimm1
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
**/ **/
UINT8 WarmThresholdCh1Dimm1; UINT8 WarmThresholdCh1Dimm1;
/** Offset 0x04D0 - Hot Threshold Ch0 Dimm0 /** Offset 0x04CD - Hot Threshold Ch0 Dimm0
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
**/ **/
UINT8 HotThresholdCh0Dimm0; UINT8 HotThresholdCh0Dimm0;
/** Offset 0x04D1 - Hot Threshold Ch0 Dimm1 /** Offset 0x04CE - Hot Threshold Ch0 Dimm1
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
**/ **/
UINT8 HotThresholdCh0Dimm1; UINT8 HotThresholdCh0Dimm1;
/** Offset 0x04D2 - Hot Threshold Ch1 Dimm0 /** Offset 0x04CF - Hot Threshold Ch1 Dimm0
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
**/ **/
UINT8 HotThresholdCh1Dimm0; UINT8 HotThresholdCh1Dimm0;
/** Offset 0x04D3 - Hot Threshold Ch1 Dimm1 /** Offset 0x04D0 - Hot Threshold Ch1 Dimm1
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
**/ **/
UINT8 HotThresholdCh1Dimm1; UINT8 HotThresholdCh1Dimm1;
/** Offset 0x04D4 - Warm Budget Ch0 Dimm0 /** Offset 0x04D1 - Warm Budget Ch0 Dimm0
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
**/ **/
UINT8 WarmBudgetCh0Dimm0; UINT8 WarmBudgetCh0Dimm0;
/** Offset 0x04D5 - Warm Budget Ch0 Dimm1 /** Offset 0x04D2 - Warm Budget Ch0 Dimm1
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
**/ **/
UINT8 WarmBudgetCh0Dimm1; UINT8 WarmBudgetCh0Dimm1;
/** Offset 0x04D6 - Warm Budget Ch1 Dimm0 /** Offset 0x04D3 - Warm Budget Ch1 Dimm0
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
**/ **/
UINT8 WarmBudgetCh1Dimm0; UINT8 WarmBudgetCh1Dimm0;
/** Offset 0x04D7 - Warm Budget Ch1 Dimm1 /** Offset 0x04D4 - Warm Budget Ch1 Dimm1
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
**/ **/
UINT8 WarmBudgetCh1Dimm1; UINT8 WarmBudgetCh1Dimm1;
/** Offset 0x04D8 - Hot Budget Ch0 Dimm0 /** Offset 0x04D5 - Hot Budget Ch0 Dimm0
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
**/ **/
UINT8 HotBudgetCh0Dimm0; UINT8 HotBudgetCh0Dimm0;
/** Offset 0x04D9 - Hot Budget Ch0 Dimm1 /** Offset 0x04D6 - Hot Budget Ch0 Dimm1
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
**/ **/
UINT8 HotBudgetCh0Dimm1; UINT8 HotBudgetCh0Dimm1;
/** Offset 0x04DA - Hot Budget Ch1 Dimm0 /** Offset 0x04D7 - Hot Budget Ch1 Dimm0
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
**/ **/
UINT8 HotBudgetCh1Dimm0; UINT8 HotBudgetCh1Dimm0;
/** Offset 0x04DB - Hot Budget Ch1 Dimm1 /** Offset 0x04D8 - Hot Budget Ch1 Dimm1
range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
**/ **/
UINT8 HotBudgetCh1Dimm1; UINT8 HotBudgetCh1Dimm1;
/** Offset 0x04DC - Idle Energy Ch0Dimm0 /** Offset 0x04D9 - Idle Energy Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/ **/
UINT8 IdleEnergyCh0Dimm0; UINT8 IdleEnergyCh0Dimm0;
/** Offset 0x04DD - Idle Energy Ch0Dimm1 /** Offset 0x04DA - Idle Energy Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/ **/
UINT8 IdleEnergyCh0Dimm1; UINT8 IdleEnergyCh0Dimm1;
/** Offset 0x04DE - Idle Energy Ch1Dimm0 /** Offset 0x04DB - Idle Energy Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/ **/
UINT8 IdleEnergyCh1Dimm0; UINT8 IdleEnergyCh1Dimm0;
/** Offset 0x04DF - Idle Energy Ch1Dimm1 /** Offset 0x04DC - Idle Energy Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/ **/
UINT8 IdleEnergyCh1Dimm1; UINT8 IdleEnergyCh1Dimm1;
/** Offset 0x04E0 - PowerDown Energy Ch0Dimm0 /** Offset 0x04DD - PowerDown Energy Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
**/ **/
UINT8 PdEnergyCh0Dimm0; UINT8 PdEnergyCh0Dimm0;
/** Offset 0x04E1 - PowerDown Energy Ch0Dimm1 /** Offset 0x04DE - PowerDown Energy Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
**/ **/
UINT8 PdEnergyCh0Dimm1; UINT8 PdEnergyCh0Dimm1;
/** Offset 0x04E2 - PowerDown Energy Ch1Dimm0 /** Offset 0x04DF - PowerDown Energy Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
**/ **/
UINT8 PdEnergyCh1Dimm0; UINT8 PdEnergyCh1Dimm0;
/** Offset 0x04E3 - PowerDown Energy Ch1Dimm1 /** Offset 0x04E0 - PowerDown Energy Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
**/ **/
UINT8 PdEnergyCh1Dimm1; UINT8 PdEnergyCh1Dimm1;
/** Offset 0x04E4 - Activate Energy Ch0Dimm0 /** Offset 0x04E1 - Activate Energy Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def) Activate Energy Contribution, range[255;0],(172= Def)
**/ **/
UINT8 ActEnergyCh0Dimm0; UINT8 ActEnergyCh0Dimm0;
/** Offset 0x04E5 - Activate Energy Ch0Dimm1 /** Offset 0x04E2 - Activate Energy Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def) Activate Energy Contribution, range[255;0],(172= Def)
**/ **/
UINT8 ActEnergyCh0Dimm1; UINT8 ActEnergyCh0Dimm1;
/** Offset 0x04E6 - Activate Energy Ch1Dimm0 /** Offset 0x04E3 - Activate Energy Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def) Activate Energy Contribution, range[255;0],(172= Def)
**/ **/
UINT8 ActEnergyCh1Dimm0; UINT8 ActEnergyCh1Dimm0;
/** Offset 0x04E7 - Activate Energy Ch1Dimm1 /** Offset 0x04E4 - Activate Energy Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def) Activate Energy Contribution, range[255;0],(172= Def)
**/ **/
UINT8 ActEnergyCh1Dimm1; UINT8 ActEnergyCh1Dimm1;
/** Offset 0x04E8 - Read Energy Ch0Dimm0 /** Offset 0x04E5 - Read Energy Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def) Read Energy Contribution, range[255;0],(212= Def)
**/ **/
UINT8 RdEnergyCh0Dimm0; UINT8 RdEnergyCh0Dimm0;
/** Offset 0x04E9 - Read Energy Ch0Dimm1 /** Offset 0x04E6 - Read Energy Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def) Read Energy Contribution, range[255;0],(212= Def)
**/ **/
UINT8 RdEnergyCh0Dimm1; UINT8 RdEnergyCh0Dimm1;
/** Offset 0x04EA - Read Energy Ch1Dimm0 /** Offset 0x04E7 - Read Energy Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def) Read Energy Contribution, range[255;0],(212= Def)
**/ **/
UINT8 RdEnergyCh1Dimm0; UINT8 RdEnergyCh1Dimm0;
/** Offset 0x04EB - Read Energy Ch1Dimm1 /** Offset 0x04E8 - Read Energy Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def) Read Energy Contribution, range[255;0],(212= Def)
**/ **/
UINT8 RdEnergyCh1Dimm1; UINT8 RdEnergyCh1Dimm1;
/** Offset 0x04EC - Write Energy Ch0Dimm0 /** Offset 0x04E9 - Write Energy Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def) Write Energy Contribution, range[255;0],(221= Def)
**/ **/
UINT8 WrEnergyCh0Dimm0; UINT8 WrEnergyCh0Dimm0;
/** Offset 0x04ED - Write Energy Ch0Dimm1 /** Offset 0x04EA - Write Energy Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def) Write Energy Contribution, range[255;0],(221= Def)
**/ **/
UINT8 WrEnergyCh0Dimm1; UINT8 WrEnergyCh0Dimm1;
/** Offset 0x04EE - Write Energy Ch1Dimm0 /** Offset 0x04EB - Write Energy Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def) Write Energy Contribution, range[255;0],(221= Def)
**/ **/
UINT8 WrEnergyCh1Dimm0; UINT8 WrEnergyCh1Dimm0;
/** Offset 0x04EF - Write Energy Ch1Dimm1 /** Offset 0x04EC - Write Energy Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def) Write Energy Contribution, range[255;0],(221= Def)
**/ **/
UINT8 WrEnergyCh1Dimm1; UINT8 WrEnergyCh1Dimm1;
/** Offset 0x04F0 - Throttler CKEMin Timer /** Offset 0x04ED - Throttler CKEMin Timer
Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
Dfault is 0x30 Dfault is 0x30
**/ **/
UINT8 ThrtCkeMinTmr; UINT8 ThrtCkeMinTmr;
/** Offset 0x04F1 - Cke Rank Mapping /** Offset 0x04EE - Cke Rank Mapping
Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies
which rank CKE[i] goes to. which rank CKE[i] goes to.
**/ **/
UINT8 CkeRankMapping; UINT8 CkeRankMapping;
/** Offset 0x04F2 - Rapl Power Floor Ch0 /** Offset 0x04EF - Rapl Power Floor Ch0
Power budget ,range[255;0],(0= 5.3W Def) Power budget ,range[255;0],(0= 5.3W Def)
**/ **/
UINT8 RaplPwrFlCh0; UINT8 RaplPwrFlCh0;
/** Offset 0x04F3 - Rapl Power Floor Ch1 /** Offset 0x04F0 - Rapl Power Floor Ch1
Power budget ,range[255;0],(0= 5.3W Def) Power budget ,range[255;0],(0= 5.3W Def)
**/ **/
UINT8 RaplPwrFlCh1; UINT8 RaplPwrFlCh1;
/** Offset 0x04F4 - Command Rate Support /** Offset 0x04F1 - Command Rate Support
CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS
**/ **/
UINT8 EnCmdRate; UINT8 EnCmdRate;
/** Offset 0x04F5 - REFRESH_2X_MODE /** Offset 0x04F2 - REFRESH_2X_MODE
0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
**/ **/
UINT8 Refresh2X; UINT8 Refresh2X;
/** Offset 0x04F6 - Energy Performance Gain /** Offset 0x04F3 - Energy Performance Gain
Enable/disable(default) Energy Performance Gain. Enable/disable(default) Energy Performance Gain.
$EN_DIS $EN_DIS
**/ **/
UINT8 EpgEnable; UINT8 EpgEnable;
/** Offset 0x04F7 - Row Hammer Solution /** Offset 0x04F4 - Row Hammer Solution
Type of method used to prevent Row Hammer. Default is Hardware RHP Type of method used to prevent Row Hammer. Default is Hardware RHP
0:Hardware RHP, 1:2x Refresh 0:Hardware RHP, 1:2x Refresh
**/ **/
UINT8 RhSolution; UINT8 RhSolution;
/** Offset 0x04F8 - User Manual Threshold /** Offset 0x04F5 - User Manual Threshold
Disabled: Predefined threshold will be used.\n Disabled: Predefined threshold will be used.\n
Enabled: User Input will be used. Enabled: User Input will be used.
$EN_DIS $EN_DIS
**/ **/
UINT8 UserThresholdEnable; UINT8 UserThresholdEnable;
/** Offset 0x04F9 - User Manual Budget /** Offset 0x04F6 - User Manual Budget
Disabled: Configuration of memories will defined the Budget value.\n Disabled: Configuration of memories will defined the Budget value.\n
Enabled: User Input will be used. Enabled: User Input will be used.
$EN_DIS $EN_DIS
**/ **/
UINT8 UserBudgetEnable; UINT8 UserBudgetEnable;
/** Offset 0x04FA - TcritMax /** Offset 0x04F7 - TcritMax
Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
has to be greater than THIGHMax .\n has to be greater than THIGHMax .\n
Critical temperature will be TcritMax Critical temperature will be TcritMax
**/ **/
UINT8 TsodTcritMax; UINT8 TsodTcritMax;
/** Offset 0x04FB - Event mode /** Offset 0x04F8 - Event mode
Disable:Comparator mode.\n Disable:Comparator mode.\n
Enable:Interrupt mode Enable:Interrupt mode
$EN_DIS $EN_DIS
**/ **/
UINT8 TsodEventMode; UINT8 TsodEventMode;
/** Offset 0x04FC - EVENT polarity /** Offset 0x04F9 - EVENT polarity
Disable:Active LOW.\n Disable:Active LOW.\n
Enable:Active HIGH Enable:Active HIGH
$EN_DIS $EN_DIS
**/ **/
UINT8 TsodEventPolarity; UINT8 TsodEventPolarity;
/** Offset 0x04FD - Critical event only /** Offset 0x04FA - Critical event only
Disable:Trips on alarm or critical.\n Disable:Trips on alarm or critical.\n
Enable:Trips only if criticaal temperature is reached Enable:Trips only if criticaal temperature is reached
$EN_DIS $EN_DIS
**/ **/
UINT8 TsodCriticalEventOnly; UINT8 TsodCriticalEventOnly;
/** Offset 0x04FE - Event output control /** Offset 0x04FB - Event output control
Disable:Event output disable.\n Disable:Event output disable.\n
Enable:Event output enabled Enable:Event output enabled
$EN_DIS $EN_DIS
**/ **/
UINT8 TsodEventOutputControl; UINT8 TsodEventOutputControl;
/** Offset 0x04FF - Alarm window lock bit /** Offset 0x04FC - Alarm window lock bit
Disable:Alarm trips are not locked and can be changed.\n Disable:Alarm trips are not locked and can be changed.\n
Enable:Alarm trips are locked and cannot be changed Enable:Alarm trips are locked and cannot be changed
$EN_DIS $EN_DIS
**/ **/
UINT8 TsodAlarmwindowLockBit; UINT8 TsodAlarmwindowLockBit;
/** Offset 0x0500 - Critical trip lock bit /** Offset 0x04FD - Critical trip lock bit
Disable:Critical trip is not locked and can be changed.\n Disable:Critical trip is not locked and can be changed.\n
Enable:Critical trip is locked and cannot be changed Enable:Critical trip is locked and cannot be changed
$EN_DIS $EN_DIS
**/ **/
UINT8 TsodCriticaltripLockBit; UINT8 TsodCriticaltripLockBit;
/** Offset 0x0501 - Shutdown mode /** Offset 0x04FE - Shutdown mode
Disable:Temperature sensor enable.\n Disable:Temperature sensor enable.\n
Enable:Temperature sensor disable Enable:Temperature sensor disable
$EN_DIS $EN_DIS
**/ **/
UINT8 TsodShutdownMode; UINT8 TsodShutdownMode;
/** Offset 0x0502 - ThighMax /** Offset 0x04FF - ThighMax
Thigh = ThighMax (Default is 93) Thigh = ThighMax (Default is 93)
**/ **/
UINT8 TsodThigMax; UINT8 TsodThigMax;
/** Offset 0x0503 - User Manual Thig and Tcrit /** Offset 0x0500 - User Manual Thig and Tcrit
Disabled(Default): Temperature will be given by the configuration of memories and Disabled(Default): Temperature will be given by the configuration of memories and
1x or 2xrefresh rate.\n 1x or 2xrefresh rate.\n
Enabled: User Input will define for Thigh and Tcrit. Enabled: User Input will define for Thigh and Tcrit.
@ -2173,32 +2168,32 @@ typedef struct {
**/ **/
UINT8 TsodManualEnable; UINT8 TsodManualEnable;
/** Offset 0x0504 - Force OLTM or 2X Refresh when needed /** Offset 0x0501 - Force OLTM or 2X Refresh when needed
Disabled(Default): = Force OLTM.\n Disabled(Default): = Force OLTM.\n
Enabled: = Force 2x Refresh. Enabled: = Force 2x Refresh.
$EN_DIS $EN_DIS
**/ **/
UINT8 ForceOltmOrRefresh2x; UINT8 ForceOltmOrRefresh2x;
/** Offset 0x0505 - Pwr Down Idle Timer /** Offset 0x0502 - Pwr Down Idle Timer
The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
AUTO: 64 for ULX/ULT, 128 for DT/Halo AUTO: 64 for ULX/ULT, 128 for DT/Halo
**/ **/
UINT8 PwdwnIdleCounter; UINT8 PwdwnIdleCounter;
/** Offset 0x0506 - Bitmask of ranks that have CA bus terminated /** Offset 0x0503 - Bitmask of ranks that have CA bus terminated
Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
Rank0 is terminating and Rank1 is non-terminating</b> Rank0 is terminating and Rank1 is non-terminating</b>
**/ **/
UINT8 CmdRanksTerminated; UINT8 CmdRanksTerminated;
/** Offset 0x0507 - GDXC MOT enable /** Offset 0x0504 - GDXC MOT enable
GDXC MOT enable. GDXC MOT enable.
$EN_DIS $EN_DIS
**/ **/
UINT8 GdxcEnable; UINT8 GdxcEnable;
/** Offset 0x0508 - PcdSerialDebugLevel /** Offset 0x0505 - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose. Info & Verbose.
@ -2207,55 +2202,71 @@ typedef struct {
**/ **/
UINT8 PcdSerialDebugLevel; UINT8 PcdSerialDebugLevel;
/** Offset 0x0509 - Fivr Faults /** Offset 0x0506 - Fivr Faults
Fivr Faults; 0: Disabled; <b>1: Enabled.</b> Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
$EN_DIS $EN_DIS
**/ **/
UINT8 FivrFaults; UINT8 FivrFaults;
/** Offset 0x050A - Fivr Efficiency /** Offset 0x0507 - Fivr Efficiency
Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b> Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
$EN_DIS $EN_DIS
**/ **/
UINT8 FivrEfficiency; UINT8 FivrEfficiency;
/** Offset 0x050B - Safe Mode Support /** Offset 0x0508 - Safe Mode Support
This option configures the varous items in the IO and MC to be more conservative.(def=Disable) This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
$EN_DIS $EN_DIS
**/ **/
UINT8 SafeMode; UINT8 SafeMode;
/** Offset 0x050C - Ask MRC to clear memory content /** Offset 0x0509 - Ask MRC to clear memory content
Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory. Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
$EN_DIS $EN_DIS
**/ **/
UINT8 CleanMemory; UINT8 CleanMemory;
/** Offset 0x050D - LpDdrDqDqsReTraining /** Offset 0x050A - LpDdrDqDqsReTraining
Enables/Disable LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining
$EN_DIS $EN_DIS
**/ **/
UINT8 LpDdrDqDqsReTraining; UINT8 LpDdrDqDqsReTraining;
/** Offset 0x050E - Post Code Output Port /** Offset 0x050B - Post Code Output Port
This option configures Post Code Output Port This option configures Post Code Output Port
**/ **/
UINT16 PostCodeOutputPort; UINT16 PostCodeOutputPort;
/** Offset 0x0510 - RMTLoopCount /** Offset 0x050D - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
**/ **/
UINT8 RMTLoopCount; UINT8 RMTLoopCount;
/** Offset 0x0511 - BER Support /** Offset 0x050E - BER Support
Enable/Disable the Rank Margin Tool interpolation/extrapolation. Enable/Disable the Rank Margin Tool interpolation/extrapolation.
0:Disable, 1:Enable 0:Disable, 1:Enable
**/ **/
UINT8 EnBER; UINT8 EnBER;
/** Offset 0x0512 /** Offset 0x050F - PEG IMR support
This option configures the IMR support for PEG.(def=Disable)
$EN_DIS
**/ **/
UINT8 ReservedFspmUpd[14]; UINT8 PegImrEnable;
/** Offset 0x0510 - PEG IMR size
The size of IMR to be allocated for PEG EndPoint device
**/
UINT16 PegImrSize;
/** Offset 0x0512 - PEG Root Port Selection
The Root Port for which the IMR to be allocated
**/
UINT8 PegImrRpSelection;
/** Offset 0x0513
**/
UINT8 ReservedFspmUpd[12];
} FSP_M_CONFIG; } FSP_M_CONFIG;
/** Fsp M Test Configuration /** Fsp M Test Configuration
@ -2480,7 +2491,7 @@ typedef struct {
/** Offset 0x0579 /** Offset 0x0579
**/ **/
UINT8 UnusedUpdSpace9; UINT8 UnusedUpdSpace10;
/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
Range: 0-65535, default is 1000. @warning Do not change from the default Range: 0-65535, default is 1000. @warning Do not change from the default
@ -2619,9 +2630,116 @@ typedef struct {
**/ **/
UINT8 KtDeviceEnable; UINT8 KtDeviceEnable;
/** Offset 0x05A5 /** Offset 0x05A5 - tRd2RdSG
Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54.
**/ **/
UINT8 ReservedFspmTestUpd[11]; UINT8 tRd2RdSG;
/** Offset 0x05A6 - tRd2RdDG
Delay between Read-to-Read commands in different Bank Group for DDR4. All other
DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
**/
UINT8 tRd2RdDG;
/** Offset 0x05A7 - tRd2RdDR
Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.
**/
UINT8 tRd2RdDR;
/** Offset 0x05A8 - tRd2RdDD
Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
**/
UINT8 tRd2RdDD;
/** Offset 0x05A9 - tWr2RdSG
Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86.
**/
UINT8 tWr2RdSG;
/** Offset 0x05AA - tWr2RdDG
Delay between Write-to-Read commands in different Bank Group for DDR4. All other
DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
**/
UINT8 tWr2RdDG;
/** Offset 0x05AB - tWr2RdDR
Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.
**/
UINT8 tWr2RdDR;
/** Offset 0x05AC - tWr2RdDD
Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
**/
UINT8 tWr2RdDD;
/** Offset 0x05AD - tWr2WrSG
Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
**/
UINT8 tWr2WrSG;
/** Offset 0x05AE - tWr2WrDG
Delay between Write-to-Write commands in different Bank Group for DDR4. All other
DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
**/
UINT8 tWr2WrDG;
/** Offset 0x05AF - tWr2WrDR
Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.
**/
UINT8 tWr2WrDR;
/** Offset 0x05B0 - tWr2WrDD
Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
**/
UINT8 tWr2WrDD;
/** Offset 0x05B1 - tRd2WrSG
Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
**/
UINT8 tRd2WrSG;
/** Offset 0x05B2 - tRd2WrDG
Delay between Read-to-Write commands in different Bank Group for DDR4. All other
DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
**/
UINT8 tRd2WrDG;
/** Offset 0x05B3 - tRd2WrDR
Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.
**/
UINT8 tRd2WrDR;
/** Offset 0x05B4 - tRd2WrDD
Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
**/
UINT8 tRd2WrDD;
/** Offset 0x05B5 - tRRD_L
Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31
**/
UINT8 tRRD_L;
/** Offset 0x05B6 - tRRD_S
Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0:
AUTO, max: 31
**/
UINT8 tRRD_S;
/** Offset 0x05B7 - tWTR_L
Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0:
AUTO, max: 60
**/
UINT8 tWTR_L;
/** Offset 0x05B8 - tWTR_S
Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only.
0: AUTO, max: 28
**/
UINT8 tWTR_S;
/** Offset 0x05B9
**/
UINT8 ReservedFspmTestUpd[3];
} FSP_M_TEST_CONFIG; } FSP_M_TEST_CONFIG;
/** Fsp M UPD Configuration /** Fsp M UPD Configuration
@ -2640,13 +2758,17 @@ typedef struct {
**/ **/
FSP_M_CONFIG FspmConfig; FSP_M_CONFIG FspmConfig;
/** Offset 0x051F
**/
UINT8 UnusedUpdSpace9;
/** Offset 0x0520 /** Offset 0x0520
**/ **/
FSP_M_TEST_CONFIG FspmTestConfig; FSP_M_TEST_CONFIG FspmTestConfig;
/** Offset 0x05B0 /** Offset 0x05BC
**/ **/
UINT16 UpdTerminator; UINT32 UpdTerminator;
} FSPM_UPD; } FSPM_UPD;
#pragma pack() #pragma pack()

166
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
View File

@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification, Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met: are permitted provided that the following conditions are met:
@ -470,9 +470,18 @@ typedef struct {
**/ **/
UINT8 PchCnviMode; UINT8 PchCnviMode;
/** Offset 0x0147 /** Offset 0x0147 - SdCard power enable polarity
Choose SD_PWREN# polarity
0: Active low, 1: Active high
**/ **/
UINT8 UnusedUpdSpace3[2]; UINT8 SdCardPowerEnableActiveHigh;
/** Offset 0x0148 - PCH USB2 PHY Power Gating enable
1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
Sus Well PG
$EN_DIS
**/
UINT8 PchUsb2PhySusPgEnable;
/** Offset 0x0149 - PCH USB OverCurrent mapping enable /** Offset 0x0149 - PCH USB OverCurrent mapping enable
1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
@ -483,7 +492,7 @@ typedef struct {
/** Offset 0x014A /** Offset 0x014A
**/ **/
UINT8 UnusedUpdSpace4; UINT8 UnusedUpdSpace3;
/** Offset 0x014B - CNVi MfUart1 Type /** Offset 0x014B - CNVi MfUart1 Type
This option configures Uart type which connects to MfUart1 This option configures Uart type which connects to MfUart1
@ -506,7 +515,7 @@ typedef struct {
/** Offset 0x014E /** Offset 0x014E
**/ **/
UINT8 UnusedUpdSpace5; UINT8 UnusedUpdSpace4;
/** Offset 0x014F - PCHHOT# pin /** Offset 0x014F - PCHHOT# pin
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
@ -594,9 +603,27 @@ typedef struct {
**/ **/
UINT16 WatchDogTimerBios; UINT16 WatchDogTimerBios;
/** Offset 0x015F /** Offset 0x015F - Remote Assistance Trigger Availablilty
Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx
$EN_DIS
**/ **/
UINT8 UnusedUpdSpace6[4]; UINT8 RemoteAssistance;
/** Offset 0x0160 - KVM Switch
Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx
$EN_DIS
**/
UINT8 AmtKvmEnabled;
/** Offset 0x0161 - KVM Switch
Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx
$EN_DIS
**/
UINT8 ForcMebxSyncUp;
/** Offset 0x0162
**/
UINT8 UnusedUpdSpace5[1];
/** Offset 0x0163 - PCH PCIe root port connection type /** Offset 0x0163 - PCH PCIe root port connection type
0: built-in device, 1:slot 0: built-in device, 1:slot
@ -604,7 +631,8 @@ typedef struct {
UINT8 PcieRpSlotImplemented[24]; UINT8 PcieRpSlotImplemented[24];
/** Offset 0x017B - Usage type for ClkSrc /** Offset 0x017B - Usage type for ClkSrc
0-23: PCH rootport, 0x40: LAN, 0x80: unspecified but in use, 0xFF: not used 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
(free running), 0xFF: not used
**/ **/
UINT8 PcieClkSrcUsage[16]; UINT8 PcieClkSrcUsage[16];
@ -631,9 +659,22 @@ typedef struct {
**/ **/
UINT16 PcieRpDetectTimeoutMs[24]; UINT16 PcieRpDetectTimeoutMs[24];
/** Offset 0x01FB /** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating
Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
PCH-H. 0: disable, 1: enable
$EN_DIS
**/ **/
UINT8 UnusedUpdSpace7[5]; UINT8 PmcModPhySusPgEnable;
/** Offset 0x01FC - SlpS0WithGbeSupport
Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable
$EN_DIS
**/
UINT8 SlpS0WithGbeSupport;
/** Offset 0x01FD
**/
UINT8 UnusedUpdSpace6[3];
/** Offset 0x0200 - Enable/Disable SA CRID /** Offset 0x0200 - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID Enable: SA CRID, Disable (Default): SA CRID
@ -642,8 +683,8 @@ typedef struct {
UINT8 CridEnable; UINT8 CridEnable;
/** Offset 0x0201 - DMI ASPM /** Offset 0x0201 - DMI ASPM
0=Disable, 3(Default)=L0sL1 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1
0:Disable, 3:L0sL1 0:Disable, 1:L0s, 2:L1, 3:L0sL1
**/ **/
UINT8 DmiAspm; UINT8 DmiAspm;
@ -689,7 +730,7 @@ typedef struct {
/** Offset 0x0219 /** Offset 0x0219
**/ **/
UINT8 UnusedUpdSpace8; UINT8 UnusedUpdSpace7;
/** Offset 0x021A - Enable or disable GNA device /** Offset 0x021A - Enable or disable GNA device
0=Disable, 1(Default)=Enable 0=Disable, 1(Default)=Enable
@ -698,7 +739,7 @@ typedef struct {
UINT8 GnaEnable; UINT8 GnaEnable;
/** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table /** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table
0=Disable/Clear, 1(Default)=Enable/Set 0=Disable/Clear, 1=Enable/Set
$EN_DIS $EN_DIS
**/ **/
UINT8 X2ApicOptOut; UINT8 X2ApicOptOut;
@ -762,11 +803,36 @@ typedef struct {
**/ **/
UINT8 DdiPortFDdc; UINT8 DdiPortFDdc;
/** Offset 0x0231 - SaPostMemProductionRsvd /** Offset 0x0231 - Enable/Disable SkipS3CdClockInit
Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
CD clock in S3 resume due to GOP absent
$EN_DIS
**/
UINT8 SkipS3CdClockInit;
/** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms
Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
T12 Delay to max 500ms
0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
**/
UINT16 DeltaT12PowerCycleDelay;
/** Offset 0x0234 - Blt Buffer Address
Address of Blt buffer
**/
UINT32 BltBufferAddress;
/** Offset 0x0238 - Blt Buffer Size
Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
**/
UINT32 BltBufferSize;
/** Offset 0x023C - SaPostMemProductionRsvd
Reserved for SA Post-Mem Production Reserved for SA Post-Mem Production
$EN_DIS $EN_DIS
**/ **/
UINT8 SaPostMemProductionRsvd[46]; UINT8 SaPostMemProductionRsvd[35];
/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable /** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
@ -888,7 +954,7 @@ typedef struct {
/** Offset 0x02BB /** Offset 0x02BB
**/ **/
UINT8 UnusedUpdSpace9[10]; UINT8 UnusedUpdSpace8[10];
/** Offset 0x02C5 - DcLoadline /** Offset 0x02C5 - DcLoadline
PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
@ -956,7 +1022,7 @@ typedef struct {
/** Offset 0x0306 /** Offset 0x0306
**/ **/
UINT8 UnusedUpdSpace10[6]; UINT8 UnusedUpdSpace9[6];
/** Offset 0x030C - Skip Multi-Processor Initialization /** Offset 0x030C - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit When this is skipped, boot loader must initialize processors before SilicionInit
@ -1021,18 +1087,24 @@ typedef struct {
**/ **/
UINT8 IslVrCmd; UINT8 IslVrCmd;
/** Offset 0x031A - ReservedCpuPostMemProduction /** Offset 0x031A - Imon slope1 correction
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
**/
UINT16 ImonSlope1[5];
/** Offset 0x0324 - ReservedCpuPostMemProduction
Reserved for CPU Post-Mem Production Reserved for CPU Post-Mem Production
$EN_DIS $EN_DIS
**/ **/
UINT8 ReservedCpuPostMemProduction[17]; UINT8 ReservedCpuPostMemProduction[1];
/** Offset 0x032B /** Offset 0x0325
**/ **/
UINT8 UnusedUpdSpace11[27]; UINT8 UnusedUpdSpace10[33];
/** Offset 0x0346 - Enable DMI ASPM /** Offset 0x0346 - Enable DMI ASPM
ASPM on PCH side of the DMI Link. Deprecated.
$EN_DIS $EN_DIS
**/ **/
UINT8 PchDmiAspm; UINT8 PchDmiAspm;
@ -1072,7 +1144,7 @@ typedef struct {
/** Offset 0x0367 /** Offset 0x0367
**/ **/
UINT8 UnusedUpdSpace12; UINT8 UnusedUpdSpace11;
/** Offset 0x0368 - VC Type /** Offset 0x0368 - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1. Virtual Channel Type Select: 0: VC0, 1: VC1.
@ -1113,7 +1185,7 @@ typedef struct {
/** Offset 0x036E /** Offset 0x036E
**/ **/
UINT8 UnusedUpdSpace13[15]; UINT8 UnusedUpdSpace12[15];
/** Offset 0x037D - Enable PCH Io Apic Entry 24-119 /** Offset 0x037D - Enable PCH Io Apic Entry 24-119
0: Disable; 1: Enable. 0: Disable; 1: Enable.
@ -1128,7 +1200,7 @@ typedef struct {
/** Offset 0x037F /** Offset 0x037F
**/ **/
UINT8 UnusedUpdSpace14; UINT8 UnusedUpdSpace13;
/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned /** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
0: Disable; 1: Enable. 0: Disable; 1: Enable.
@ -1228,7 +1300,7 @@ typedef struct {
/** Offset 0x0390 /** Offset 0x0390
**/ **/
UINT8 UnusedUpdSpace15[3]; UINT8 UnusedUpdSpace14[3];
/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK /** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
@ -1320,10 +1392,9 @@ typedef struct {
**/ **/
UINT8 PcieRpMaxPayload[24]; UINT8 PcieRpMaxPayload[24];
/** Offset 0x04E6 - PCIE RP Device Reset Pad Active High /** Offset 0x04E6
Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad.
**/ **/
UINT8 PcieRpDeviceResetPadActiveHigh[24]; UINT8 UnusedUpdSpace15[24];
/** Offset 0x04FE - PCIE RP Pcie Speed /** Offset 0x04FE - PCIE RP Pcie Speed
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
@ -1332,8 +1403,8 @@ typedef struct {
UINT8 PcieRpPcieSpeed[24]; UINT8 PcieRpPcieSpeed[24];
/** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method /** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method
PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search; PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
4: Fixed Coeficients. 1: hardware equalization; 4: Fixed Coeficients.
**/ **/
UINT8 PcieRpGen3EqPh3Method[24]; UINT8 PcieRpGen3EqPh3Method[24];
@ -1347,15 +1418,9 @@ typedef struct {
**/ **/
UINT8 PcieRpCompletionTimeout[24]; UINT8 PcieRpCompletionTimeout[24];
/** Offset 0x055E - PCIE RP Device Reset Pad /** Offset 0x055E
The PCH pin assigned to device PERST# signal if available, zero otherwise. See
also DeviceResetPadActiveHigh.
**/ **/
UINT32 PcieRpDeviceResetPad[24]; UINT8 UnusedUpdSpace16[106];
/** Offset 0x05BE
**/
UINT8 UnusedUpdSpace16[10];
/** Offset 0x05C8 - PCIE RP Aspm /** Offset 0x05C8 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
@ -1550,6 +1615,7 @@ typedef struct {
/** Offset 0x0680 - PCH Pm Lpc Clock Run /** Offset 0x0680 - PCH Pm Lpc Clock Run
This member describes whether or not the LPC ClockRun feature of PCH should be enabled. This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
Default value is Disabled
$EN_DIS $EN_DIS
**/ **/
UINT8 PchPmLpcClockRun; UINT8 PchPmLpcClockRun;
@ -1771,7 +1837,7 @@ typedef struct {
UINT8 SataRstPcieDeviceResetDelay[3]; UINT8 SataRstPcieDeviceResetDelay[3];
/** Offset 0x06F5 - Enable eMMC HS400 Training /** Offset 0x06F5 - Enable eMMC HS400 Training
Determine if HS400 Training is required. Deprecated.
$EN_DIS $EN_DIS
**/ **/
UINT8 PchScsEmmcHs400TuningRequired; UINT8 PchScsEmmcHs400TuningRequired;
@ -1793,7 +1859,7 @@ typedef struct {
UINT8 PchScsEmmcHs400TxDataDll; UINT8 PchScsEmmcHs400TxDataDll;
/** Offset 0x06F9 - I/O Driver Strength /** Offset 0x06F9 - I/O Driver Strength
I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm. Deprecated.
0:33 Ohm, 1:40 Ohm, 2:50 Ohm 0:33 Ohm, 1:40 Ohm, 2:50 Ohm
**/ **/
UINT8 PchScsEmmcHs400DriverStrength; UINT8 PchScsEmmcHs400DriverStrength;
@ -2192,9 +2258,15 @@ typedef struct {
**/ **/
UINT8 PmcCpuC10GatePinEnable; UINT8 PmcCpuC10GatePinEnable;
/** Offset 0x07AB /** Offset 0x07AB - Pch Dmi Aspm Ctrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
**/ **/
UINT8 ReservedFspsUpd[2]; UINT8 PchDmiAspmCtrl;
/** Offset 0x07AC
**/
UINT8 ReservedFspsUpd[1];
} FSP_S_CONFIG; } FSP_S_CONFIG;
/** Fsp S Test Configuration /** Fsp S Test Configuration
@ -2634,13 +2706,13 @@ typedef struct {
UINT8 C1e; UINT8 C1e;
/** Offset 0x080D - Enable or Disable Package Cstate Demotion /** Offset 0x080D - Enable or Disable Package Cstate Demotion
Enable or Disable Package Cstate Demotion. 0: Disable; <b>1: Enable</b> Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable
$EN_DIS $EN_DIS
**/ **/
UINT8 PkgCStateDemotion; UINT8 PkgCStateDemotion;
/** Offset 0x080E - Enable or Disable Package Cstate UnDemotion /** Offset 0x080E - Enable or Disable Package Cstate UnDemotion
Enable or Disable Package Cstate UnDemotion. 0: Disable; <b>1: Enable</b> Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable
$EN_DIS $EN_DIS
**/ **/
UINT8 PkgCStateUnDemotion; UINT8 PkgCStateUnDemotion;
@ -3111,7 +3183,7 @@ typedef struct {
UINT8 UnusedUpdSpace26[17]; UINT8 UnusedUpdSpace26[17];
/** Offset 0x0A72 - Skip POSTBOOT SAI /** Offset 0x0A72 - Skip POSTBOOT SAI
This skip the Post Boot Sai programming. 0: Set Post Boot Sai; 1: Skip Post Boot Sai. Deprecated
$EN_DIS $EN_DIS
**/ **/
UINT8 SkipPostBootSai; UINT8 SkipPostBootSai;