soc/intel/alderlake: Set LpmStateEnableMask UPD

Use the get_supported_lpm_states() function to set the respective FSP
UPD.

TEST=with patchtrain on brya0,
/sys/kernel/debug/pmc_core/substate_requirements shows only the
substates that are applicable to the design (S0i2.0, S0i3.0).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Tim Wawrzynczak 2021-07-19 15:35:47 -06:00
parent 6cf79d9d14
commit e2b8f30bee
4 changed files with 35 additions and 0 deletions

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@ -116,6 +116,20 @@ enum pkgcstate_limit {
LIMIT_AUTO = 255,
};
/* Bit values for use in LpmStateEnableMask. */
enum lpm_state_mask {
LPM_S0i2_0 = BIT(0),
LPM_S0i2_1 = BIT(1),
LPM_S0i2_2 = BIT(2),
LPM_S0i3_0 = BIT(3),
LPM_S0i3_1 = BIT(4),
LPM_S0i3_2 = BIT(5),
LPM_S0i3_3 = BIT(6),
LPM_S0i3_4 = BIT(7),
LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
| LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
};
struct soc_intel_alderlake_config {
/* Common struct containing soc config data required by common code */

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@ -188,3 +188,18 @@ enum adl_cpu_type get_adl_cpu_type(void)
return ADL_UNKNOWN;
}
uint8_t get_supported_lpm_mask(void)
{
enum adl_cpu_type type = get_adl_cpu_type();
switch (type) {
case ADL_M: /* fallthrough */
case ADL_P:
return LPM_S0i2_0 | LPM_S0i3_0;
case ADL_S:
return LPM_S0i2_0 | LPM_S0i2_1;
default:
printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type);
return 0;
}
}

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@ -15,6 +15,7 @@
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <intelblocks/tcss.h>
#include <soc/cpu.h>
#include <soc/gpio_soc_defs.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
@ -614,6 +615,8 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
/* VrConfig Settings for IA and GT domains */
for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]);
s_cfg->LpmStateEnableMask = get_supported_lpm_mask();
}
static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,

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@ -28,4 +28,7 @@ enum adl_cpu_type {
enum adl_cpu_type get_adl_cpu_type(void);
/* Get a bitmask of supported LPM states */
uint8_t get_supported_lpm_mask(void);
#endif