nb/amd/agesa: Get rid of device_t
Change-Id: I5bd1c1cd71bd9541c1a95d444cd8d5ff40687dde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26436 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -38,13 +38,13 @@
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#define FX_DEVS 1
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static device_t __f0_dev[FX_DEVS];
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static device_t __f1_dev[FX_DEVS];
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static device_t __f2_dev[FX_DEVS];
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static device_t __f4_dev[FX_DEVS];
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static struct device *__f0_dev[FX_DEVS];
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static struct device *__f1_dev[FX_DEVS];
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static struct device *__f2_dev[FX_DEVS];
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static struct device *__f4_dev[FX_DEVS];
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static unsigned fx_devs = 0;
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static device_t get_node_pci(u32 nodeid, u32 fn)
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static struct device *get_node_pci(u32 nodeid, u32 fn)
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{
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if ((CONFIG_CDB + nodeid) < 32) {
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return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
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@ -355,7 +355,7 @@ static void set_resource(struct device *dev, struct resource *resource,
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}
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#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
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extern device_t vga_pri; // the primary vga device, defined in device.c
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extern struct device *vga_pri; // the primary vga device, defined in device.c
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#endif
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static void create_vga_resource(struct device *dev, unsigned nodeid)
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@ -618,7 +618,7 @@ static void cpu_bus_init(struct device *dev)
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/* North Bridge Structures */
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static void northbridge_fill_ssdt_generator(device_t device)
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static void northbridge_fill_ssdt_generator(struct device *device)
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{
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msr_t msr;
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char pscope[] = "\\_SB.PCI0";
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@ -659,7 +659,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
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return (unsigned long)current;
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}
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static unsigned long agesa_write_acpi_tables(device_t device,
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static unsigned long agesa_write_acpi_tables(struct device *device,
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unsigned long current,
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acpi_rsdp_t *rsdp)
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{
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@ -19,7 +19,7 @@
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#include <device/pci_ops.h>
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#include <lib.h>
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static void iommu_read_resources(device_t dev)
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static void iommu_read_resources(struct device *dev)
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{
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struct resource *res;
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@ -35,7 +35,7 @@ static void iommu_read_resources(device_t dev)
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res->flags = IORESOURCE_MEM;
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}
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static void iommu_set_resources(device_t dev)
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static void iommu_set_resources(struct device *dev)
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{
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struct resource *res;
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@ -49,15 +49,15 @@ typedef struct dram_base_mask {
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static unsigned node_nums;
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static unsigned sblink;
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static device_t __f0_dev[MAX_NODE_NUMS];
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static device_t __f1_dev[MAX_NODE_NUMS];
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static device_t __f2_dev[MAX_NODE_NUMS];
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static device_t __f4_dev[MAX_NODE_NUMS];
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static struct device *__f0_dev[MAX_NODE_NUMS];
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static struct device *__f1_dev[MAX_NODE_NUMS];
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static struct device *__f2_dev[MAX_NODE_NUMS];
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static struct device *__f4_dev[MAX_NODE_NUMS];
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static unsigned fx_devs = 0;
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static dram_base_mask_t get_dram_base_mask(u32 nodeid)
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{
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device_t dev;
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struct device *dev;
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dram_base_mask_t d;
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dev = __f1_dev[0];
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u32 temp;
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@ -73,7 +73,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
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return d;
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}
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static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
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static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
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u32 io_min, u32 io_max)
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{
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u32 i;
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@ -100,7 +100,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
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pci_write_config32(__f1_dev[i], reg, tempreg);
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}
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static device_t get_node_pci(u32 nodeid, u32 fn)
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static struct device *get_node_pci(u32 nodeid, u32 fn)
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{
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#if MAX_NODE_NUMS + CONFIG_CDB >= 32
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if ((CONFIG_CDB + nodeid) < 32) {
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@ -143,7 +143,7 @@ static void f1_write_config32(unsigned reg, u32 value)
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if (fx_devs == 0)
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get_fx_devs();
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for (i = 0; i < fx_devs; i++) {
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device_t dev;
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struct device *dev;
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dev = __f1_dev[i];
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if (dev && dev->enabled) {
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pci_write_config32(dev, reg, value);
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@ -451,7 +451,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
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return (unsigned long)current;
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}
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static void northbridge_fill_ssdt_generator(device_t device)
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static void northbridge_fill_ssdt_generator(struct device *device)
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{
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msr_t msr;
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char pscope[] = "\\_SB.PCI0";
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@ -472,7 +472,7 @@ static void northbridge_fill_ssdt_generator(device_t device)
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acpigen_pop_len();
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}
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static unsigned long agesa_write_acpi_tables(device_t device,
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static unsigned long agesa_write_acpi_tables(struct device *device,
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unsigned long current,
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acpi_rsdp_t *rsdp)
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{
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@ -604,7 +604,7 @@ static void domain_read_resources(struct device *dev)
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/* Is this register allocated? */
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if ((base & 3) != 0) {
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unsigned nodeid, reg_link;
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device_t reg_dev;
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struct device *reg_dev;
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if (reg < 0xc0) { // mmio
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nodeid = (limit & 0xf) + (base&0x30);
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} else { // io
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@ -786,7 +786,7 @@ static struct device_operations pci_domain_ops = {
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.scan_bus = pci_domain_scan_bus,
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};
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static void sysconf_init(device_t dev) // first node
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static void sysconf_init(struct device *dev) // first node
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{
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sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
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node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
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@ -828,12 +828,12 @@ static void add_more_links(struct device *dev, unsigned total_links)
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last->next = NULL;
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}
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static void cpu_bus_scan(device_t dev)
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static void cpu_bus_scan(struct device *dev)
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{
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struct bus *cpu_bus;
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device_t dev_mc;
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struct device *dev_mc;
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#if CONFIG_CBB
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device_t pci_domain;
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struct device *pci_domain;
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#endif
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int i,j;
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int coreid_bits;
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@ -913,7 +913,7 @@ static void cpu_bus_scan(device_t dev)
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/* Find which cpus are present */
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cpu_bus = dev->link_list;
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for (i = 0; i < node_nums; i++) {
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device_t cdb_dev;
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struct device *cdb_dev;
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unsigned busn, devn;
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struct bus *pbus;
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@ -997,7 +997,7 @@ static void cpu_bus_scan(device_t dev)
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printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
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i, j, apic_id);
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device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
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struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
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if (cpu)
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amd_cpu_topology(cpu, i, j);
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} //j
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@ -48,15 +48,15 @@ typedef struct dram_base_mask {
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static unsigned node_nums;
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static unsigned sblink;
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static device_t __f0_dev[MAX_NODE_NUMS];
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static device_t __f1_dev[MAX_NODE_NUMS];
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static device_t __f2_dev[MAX_NODE_NUMS];
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static device_t __f4_dev[MAX_NODE_NUMS];
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static struct device *__f0_dev[MAX_NODE_NUMS];
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static struct device *__f1_dev[MAX_NODE_NUMS];
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static struct device *__f2_dev[MAX_NODE_NUMS];
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static struct device *__f4_dev[MAX_NODE_NUMS];
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static unsigned fx_devs = 0;
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static dram_base_mask_t get_dram_base_mask(u32 nodeid)
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{
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device_t dev;
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struct device *dev;
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dram_base_mask_t d;
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dev = __f1_dev[0];
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u32 temp;
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@ -72,7 +72,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
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return d;
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}
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static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
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static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
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u32 io_min, u32 io_max)
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{
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u32 i;
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@ -99,7 +99,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
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pci_write_config32(__f1_dev[i], reg, tempreg);
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}
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static device_t get_node_pci(u32 nodeid, u32 fn)
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static struct device *get_node_pci(u32 nodeid, u32 fn)
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{
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#if MAX_NODE_NUMS + CONFIG_CDB >= 32
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if ((CONFIG_CDB + nodeid) < 32) {
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@ -142,7 +142,7 @@ static void f1_write_config32(unsigned reg, u32 value)
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if (fx_devs == 0)
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get_fx_devs();
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for (i = 0; i < fx_devs; i++) {
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device_t dev;
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struct device *dev;
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dev = __f1_dev[i];
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if (dev && dev->enabled) {
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pci_write_config32(dev, reg, value);
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}
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}
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static u32 amdfam16_nodeid(device_t dev)
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static u32 amdfam16_nodeid(struct device *dev)
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{
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#if MAX_NODE_NUMS == 64
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unsigned busn;
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@ -185,7 +185,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
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* @retval 0 resource exists, not usable
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* @retval 1 resource exist, resource has been allocated before
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*/
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static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
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static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
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unsigned goal_link)
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{
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struct resource *res;
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@ -193,7 +193,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
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int result;
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res = 0;
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for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
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device_t dev;
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struct device *dev;
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dev = __f0_dev[nodeid];
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if (!dev)
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continue;
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@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
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return result;
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}
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static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link)
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static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
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{
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struct resource *resource;
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u32 free_reg, reg;
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@ -240,7 +240,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi
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return resource;
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}
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static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link)
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static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link)
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{
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struct resource *resource;
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u32 free_reg, reg;
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@ -266,7 +266,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link
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return resource;
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}
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static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
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static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link)
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{
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struct resource *resource;
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@ -308,7 +308,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
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}
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static void read_resources(device_t dev)
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static void read_resources(struct device *dev)
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{
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u32 nodeid;
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struct bus *link;
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@ -328,7 +328,7 @@ static void read_resources(device_t dev)
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mmconf_resource(dev, 0xc0010058);
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}
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static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
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static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
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{
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resource_t rbase, rend;
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unsigned reg, link_num;
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@ -379,7 +379,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
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* but it is too difficult to deal with the resource allocation magic.
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*/
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static void create_vga_resource(device_t dev, unsigned nodeid)
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static void create_vga_resource(struct device *dev, unsigned nodeid)
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{
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struct bus *link;
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@ -388,7 +388,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
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for (link = dev->link_list; link; link = link->next) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
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extern device_t vga_pri; // the primary vga device, defined in device.c
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extern struct device *vga_pri; // the primary vga device, defined in device.c
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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link->secondary,link->subordinate);
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/* We need to make sure the vga_pri is under the link */
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@ -407,7 +407,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
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set_vga_enable_reg(nodeid, sblink);
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}
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static void set_resources(device_t dev)
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static void set_resources(struct device *dev)
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{
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unsigned nodeid;
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struct bus *bus;
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@ -451,7 +451,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
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return (unsigned long)current;
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}
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static void northbridge_fill_ssdt_generator(device_t device)
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static void northbridge_fill_ssdt_generator(struct device *device)
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{
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msr_t msr;
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char pscope[] = "\\_SB.PCI0";
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@ -472,7 +472,7 @@ static void northbridge_fill_ssdt_generator(device_t device)
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acpigen_pop_len();
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}
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static unsigned long agesa_write_acpi_tables(device_t device,
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static unsigned long agesa_write_acpi_tables(struct device *device,
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unsigned long current,
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acpi_rsdp_t *rsdp)
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{
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@ -587,7 +587,7 @@ static const struct pci_driver family10_northbridge __pci_driver = {
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static void fam16_finalize(void *chip_info)
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{
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device_t dev;
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struct device *dev;
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u32 value;
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dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
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pci_write_config32(dev, 0xF8, 0);
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@ -606,7 +606,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = {
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.final = fam16_finalize,
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};
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static void domain_read_resources(device_t dev)
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static void domain_read_resources(struct device *dev)
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{
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unsigned reg;
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@ -619,7 +619,7 @@ static void domain_read_resources(device_t dev)
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/* Is this register allocated? */
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if ((base & 3) != 0) {
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unsigned nodeid, reg_link;
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device_t reg_dev;
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struct device *reg_dev;
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if (reg < 0xc0) { // mmio
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nodeid = (limit & 0xf) + (base&0x30);
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} else { // io
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@ -692,7 +692,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
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}
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#endif
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static void domain_set_resources(device_t dev)
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static void domain_set_resources(struct device *dev)
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{
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unsigned long mmio_basek;
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u32 pci_tolm;
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@ -811,13 +811,13 @@ static struct device_operations pci_domain_ops = {
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.acpi_name = domain_acpi_name,
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};
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static void sysconf_init(device_t dev) // first node
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static void sysconf_init(struct device *dev) // first node
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{
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sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
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node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
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}
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static void add_more_links(device_t dev, unsigned total_links)
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static void add_more_links(struct device *dev, unsigned total_links)
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{
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struct bus *link, *last = NULL;
|
||||
int link_num;
|
||||
|
@ -853,12 +853,12 @@ static void add_more_links(device_t dev, unsigned total_links)
|
|||
last->next = NULL;
|
||||
}
|
||||
|
||||
static void cpu_bus_scan(device_t dev)
|
||||
static void cpu_bus_scan(struct device *dev)
|
||||
{
|
||||
struct bus *cpu_bus;
|
||||
device_t dev_mc;
|
||||
struct device *dev_mc;
|
||||
#if CONFIG_CBB
|
||||
device_t pci_domain;
|
||||
struct device *pci_domain;
|
||||
#endif
|
||||
int i,j;
|
||||
int coreid_bits;
|
||||
|
@ -938,7 +938,7 @@ static void cpu_bus_scan(device_t dev)
|
|||
/* Find which cpus are present */
|
||||
cpu_bus = dev->link_list;
|
||||
for (i = 0; i < node_nums; i++) {
|
||||
device_t cdb_dev;
|
||||
struct device *cdb_dev;
|
||||
unsigned busn, devn;
|
||||
struct bus *pbus;
|
||||
|
||||
|
@ -1022,14 +1022,14 @@ static void cpu_bus_scan(device_t dev)
|
|||
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
|
||||
i, j, apic_id);
|
||||
|
||||
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
|
||||
struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
|
||||
if (cpu)
|
||||
amd_cpu_topology(cpu, i, j);
|
||||
} //j
|
||||
}
|
||||
}
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
static void cpu_bus_init(struct device *dev)
|
||||
{
|
||||
initialize_cpus(dev->link_list);
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue