mb/qemu/x86: Remove option for LEGACY_SMP_INIT
This is deprecated after the 4.18 release. Change-Id: I17327c31f8ade51716578e45c2d90a327efcd4ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69128 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
parent
03a6ccd20d
commit
e2d291b5ae
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@ -10,19 +10,6 @@ config CPU_QEMU_X86
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if CPU_QEMU_X86
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choice
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prompt "AP init"
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default CPU_QEMU_X86_LAPIC_INIT
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config CPU_QEMU_X86_LAPIC_INIT
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bool "Legacy serial LAPIC init"
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select LEGACY_SMP_INIT
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config CPU_QEMU_X86_PARALLEL_MP
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bool "Parallel MP init"
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endchoice
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# coreboot i440fx does not support SMM
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choice
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prompt "SMM support"
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@ -40,7 +27,6 @@ config CPU_QEMU_X86_ASEG_SMM
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config CPU_QEMU_X86_TSEG_SMM
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bool "SMM in TSEG"
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select SMM_TSEG
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depends on CPU_QEMU_X86_PARALLEL_MP
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endchoice
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@ -26,9 +26,6 @@ ifneq ($(CONFIG_BOARD_EMULATION_QEMU_X86_Q35),y)
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ramstage-y += madt.c
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endif
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ramstage-$(CONFIG_SMM_LEGACY_ASEG) += smi.c
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ramstage-$(CONFIG_SMM_LEGACY_ASEG) += ../../../cpu/x86/smm/smmrelocate.S
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CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include
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endif
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@ -374,12 +374,6 @@ static void lpc_init(struct device *dev)
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i8259_configure_irq_trigger(9, 1);
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i82801ix_set_acpi_mode(dev);
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/* Don't allow evil boot loaders, kernels, or
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* userspace applications to deceive us:
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*/
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if (CONFIG(SMM_LEGACY_ASEG))
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aseg_smm_lock();
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}
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static void i82801ix_lpc_read_resources(struct device *dev)
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@ -1,162 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <acpi/acpi.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <cpu/x86/smi_deprecated.h>
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#include <string.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801ix.h"
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/* I945/GM45 */
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#define SMRAM 0x9d
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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static u16 pmbase = DEFAULT_PMBASE;
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extern uint8_t smm_relocation_start, smm_relocation_end;
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static void *default_smm_area = NULL;
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static void aseg_smm_relocate(void)
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{
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u32 smi_en;
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u16 pm1_en;
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printk(BIOS_DEBUG, "Initializing SMM handler...");
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pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), D31F0_PMBASE) &
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0xfffc;
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
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smi_en = inl(pmbase + SMI_EN);
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if (smi_en & GBL_SMI_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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default_smm_area = backup_default_smm_area();
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/* copy the SMM relocation code */
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memcpy((void *)0x38000, &smm_relocation_start,
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&smm_relocation_end - &smm_relocation_start);
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wbinvd();
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printk(BIOS_DEBUG, "\n");
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dump_smi_status(reset_smi_status());
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dump_pm1_status(reset_pm1_status());
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dump_gpe0_status(reset_gpe0_status());
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dump_alt_gp_smi_status(reset_alt_gp_smi_status());
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dump_tco_status(reset_tco_status());
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/* Enable SMI generation:
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* - on TCO events
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* - on APMC writes (io 0xb2)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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*/
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smi_en = 0; /* reset SMI enables */
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smi_en |= TCO_EN;
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smi_en |= APMC_EN;
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if (CONFIG(DEBUG_PERIODIC_SMI))
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smi_en |= PERIODIC_EN;
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smi_en |= BIOS_EN;
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/* The following need to be on for SMIs to happen */
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smi_en |= EOS | GBL_SMI_EN;
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outl(smi_en, pmbase + SMI_EN);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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outw(pm1_en, pmbase + PM1_EN);
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/**
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* There are several methods of raising a controlled SMI# via
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* software, among them:
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local APIC is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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* I'm not too worried about the better of the methods at the moment
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*/
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/* raise an SMI interrupt */
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printk(BIOS_SPEW, " ... raise SMI#\n");
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apm_control(APM_CNT_NOOP_SMI);
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}
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static int smm_handler_copied = 0;
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static void aseg_smm_install(void)
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{
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/* The first CPU running this gets to copy the SMM handler. But not all
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* of them.
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*/
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if (smm_handler_copied)
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return;
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smm_handler_copied = 1;
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/* if we're resuming from S3, the SMM code is already in place,
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* so don't copy it again to keep the current SMM state */
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if (!acpi_is_wakeup_s3()) {
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/* enable the SMM memory window */
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pci_write_config8(pcidev_on_root(0, 0), SMRAM,
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D_OPEN | G_SMRAME | C_BASE_SEG);
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/* copy the real SMM handler */
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memcpy((void *)0xa0000, _binary_smm_start,
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_binary_smm_end - _binary_smm_start);
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wbinvd();
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}
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/* close the SMM memory window and enable normal SMM */
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pci_write_config8(pcidev_on_root(0, 0), SMRAM,
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G_SMRAME | C_BASE_SEG);
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}
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void smm_init(void)
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{
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/* Put SMM code to 0xa0000 */
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aseg_smm_install();
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/* Put relocation code to 0x38000 and relocate SMBASE */
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aseg_smm_relocate();
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/* We're done. Make sure SMIs can happen! */
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smi_set_eos();
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}
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void smm_init_completion(void)
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{
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restore_default_smm_area(default_smm_area);
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}
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void aseg_smm_lock(void)
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{
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/* LOCK the SMM memory window and enable normal SMM.
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* After running this function, only a full reset can
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(pcidev_on_root(0, 0), SMRAM,
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D_LCK | G_SMRAME | C_BASE_SEG);
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}
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@ -9,11 +9,6 @@
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#include <soc/nvs.h>
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#if CONFIG(SMM_LEGACY_ASEG)
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/* For qemu/x86-q35 to build properly. */
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struct global_nvs *gnvs;
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#endif
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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