nb/intel/haswell/haswell.h: Do not include `pch.h`

Avoid indirect header inclusion, include `pch.h` where necessary.

Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/northbridge/intel/haswell/gma.c

@@ -15,6 +15,7 @@
 #include <drivers/intel/gma/libgfxinit.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <drivers/intel/gma/opregion.h>
+#include <southbridge/intel/lynxpoint/pch.h>
 #include <string.h>
 #include <types.h>
 

src/northbridge/intel/haswell/haswell.h

@@ -10,8 +10,6 @@
 
 #include "memmap.h"
 
-#include <southbridge/intel/lynxpoint/pch.h>
-
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
 

src/northbridge/intel/haswell/northbridge.c

@@ -13,6 +13,7 @@
 #include <device/pci_ops.h>
 #include <boot/tables.h>
 #include <security/intel/txt/txt_register.h>
+#include <southbridge/intel/lynxpoint/pch.h>
 
 #include "chip.h"
 #include "haswell.h"

src/southbridge/intel/lynxpoint/acpi/lpc.asl

@@ -2,6 +2,8 @@
 
 // Intel LPC Bus Device  - 0:1f.0
 
+#include <southbridge/intel/lynxpoint/pch.h>
+
 Device (LPCB)
 {
 	Name (_ADR, 0x001f0000)