vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
Also document the maximum nuber of lanes for the different platforms. Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -123,7 +123,16 @@ typedef struct __packed {
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* GPP[5:4] | [1:0] | PCIe, XGBE
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* GPP[7:6] | [3:2] | PCIe, SATA
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*
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* Dali has less DXIO connectivity than Picasso:
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* Picasso supports up to 7 PCIe ports. The 8 GFX PCIe lanes can either be used as an x8 port
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* or split into two x4 ports. The GPP general purpose lanes can be used as PCIe x4, x2 and x1
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* ports. The ports can only start at logical lane numbers that are integer multiples of the
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* lane width, so for example an x4 port can only start with the logical lane 0, 4, 8 or 12.
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* Different ports mustn't overlap or be assigned to the same lane(s). Within ports with the
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* same width the one with a higher start logical lane number needs to be assigned to a higher
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* PCIe root port number; ports of the same size don't have to be assigned to consecutive PCIe
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* root ports though.
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*
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* Dali only supports up to 5 PCIe ports and has less DXIO connectivity than Picasso:
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*
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* physical | logical | protocol
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* ---------|---------|-----------
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