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Port of CS5536 early UART setup from v3. 

Permit early setup of COM2

Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Edwin Beasant 2010-02-09 10:22:33 +00:00 committed by Patrick Georgi
parent 37d8c215a2
commit e30db0e370
5 changed files with 117 additions and 48 deletions
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2
src/mainboard/amd/norwich/romstage.c
View File

@ -115,7 +115,7 @@ void cache_as_ram_main(void)
* up later... * up later...
*/ */
/* If debug. real setup done in chipset init via Config.lb. */ /* If debug. real setup done in chipset init via Config.lb. */
cs5536_setup_onchipuart(); cs5536_setup_onchipuart(1);
mb_gpio_init(); mb_gpio_init();
uart_init(); uart_init();
console_init(); console_init();

2
src/mainboard/olpc/btest/romstage.c
View File

@ -177,7 +177,7 @@ static void main(unsigned long bist)
* it is counting on some early MSR setup * it is counting on some early MSR setup
* for cs5536 * for cs5536
*/ */
cs5536_setup_onchipuart(); cs5536_setup_onchipuart(1);
gpio_init(); gpio_init();
uart_init(); uart_init();
console_init(); console_init();

2
src/mainboard/olpc/rev_a/romstage.c
View File

@ -177,7 +177,7 @@ static void main(unsigned long bist)
* it is counting on some early MSR setup * it is counting on some early MSR setup
* for cs5536 * for cs5536
*/ */
cs5536_setup_onchipuart(); cs5536_setup_onchipuart(1);
gpio_init(); gpio_init();
uart_init(); uart_init();
console_init(); console_init();

82
src/southbridge/amd/cs5536/cs5536.c
View File

@ -248,37 +248,44 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
isa_dma_init(); isa_dma_init();
} }
/**
* Depending on settings in the config struct, enable COM1 or COM2 or both.
*
* If the enable is NOT set, the UARTs are explicitly disabled, which is
* required if (e.g.) there is a Super I/O attached that does COM1 or COM2.
*
* @param sb Southbridge config structure.
*/
static void uarts_init(struct southbridge_amd_cs5536_config *sb) static void uarts_init(struct southbridge_amd_cs5536_config *sb)
{ {
msr_t msr; msr_t msr;
uint16_t addr; u16 addr = 0;
uint32_t gpio_addr; u32 gpio_addr;
device_t dev; device_t dev;
dev = dev_find_device(PCI_VENDOR_ID_AMD, dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_ISA, 0); PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
gpio_addr &= ~1; /* clear IO bit */ gpio_addr &= ~1; /* Clear I/O bit */
printk_debug("GPIO_ADDR: %08X\n", gpio_addr); printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);
/* This could be extended to support IR modes */ /* This could be extended to support IR modes. */
/* COM1 */ /* COM1 */
if (sb->com1_enable) { if (sb->com1_enable) {
/* Set the address */ printk(BIOS_SPEW, "uarts_init: enable COM1\n");
/* Set the address. */
switch (sb->com1_address) { switch (sb->com1_address) {
case 0x3F8: case 0x3F8:
addr = 7; addr = 7;
break; break;
case 0x3E8: case 0x3E8:
addr = 6; addr = 6;
break; break;
case 0x2F8: case 0x2F8:
addr = 5; addr = 5;
break; break;
case 0x2E8: case 0x2E8:
addr = 4; addr = 4;
break; break;
@ -287,13 +294,13 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
msr.lo |= addr << 16; msr.lo |= addr << 16;
wrmsr(MDD_LEG_IO, msr); wrmsr(MDD_LEG_IO, msr);
/* Set the IRQ */ /* Set the IRQ. */
msr = rdmsr(MDD_IRQM_YHIGH); msr = rdmsr(MDD_IRQM_YHIGH);
msr.lo |= sb->com1_irq << 24; msr.lo |= sb->com1_irq << 24;
wrmsr(MDD_IRQM_YHIGH, msr); wrmsr(MDD_IRQM_YHIGH, msr);
/* GPIO8 - UART1_TX */ /* GPIO8 - UART1_TX */
/* Set: Output Enable (0x4) */ /* Set: Output Enable (0x4) */
outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */ /* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
@ -301,28 +308,31 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
/* GPIO9 - UART1_RX */ /* GPIO9 - UART1_RX */
/* Set: Input Enable (0x20) */ /* Set: Input Enable (0x20) */
outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE); outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE);
/* Set: INAUX1 Select (0x34) */ /* Set: INAUX1 Select (0x34) */
outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
/* Set: GPIO 8 + 9 Pull Up (0x18) */ /* Set: GPIO 8 + 9 Pull Up (0x18) */
outl(GPIOL_8_SET | GPIOL_9_SET, outl(GPIOL_8_SET | GPIOL_9_SET,
gpio_addr + GPIOL_PULLUP_ENABLE); gpio_addr + GPIOL_PULLUP_ENABLE);
/* enable COM1 */ /* Enable COM1.
/* Bit 1 = device enable Bit 4 = allow access to the upper banks */ *
* Bit 1 = device enable
* Bit 4 = allow access to the upper banks
*/
msr.lo = (1 << 4) | (1 << 1); msr.lo = (1 << 4) | (1 << 1);
msr.hi = 0; msr.hi = 0;
wrmsr(MDD_UART1_CONF, msr); wrmsr(MDD_UART1_CONF, msr);
} else { } else {
/* Reset and disable COM1 */ /* Reset and disable COM1. */
printk(BIOS_SPEW, "uarts_init: disable COM1\n");
msr = rdmsr(MDD_UART1_CONF); msr = rdmsr(MDD_UART1_CONF);
msr.lo = 1; // reset msr.lo = 1; /* Reset */
wrmsr(MDD_UART1_CONF, msr); wrmsr(MDD_UART1_CONF, msr);
msr.lo = 0; // disabled msr.lo = 0; /* Disabled */
wrmsr(MDD_UART1_CONF, msr); wrmsr(MDD_UART1_CONF, msr);
/* Disable the IRQ */ /* Disable the IRQ. */
msr = rdmsr(MDD_LEG_IO); msr = rdmsr(MDD_LEG_IO);
msr.lo &= ~(0xF << 16); msr.lo &= ~(0xF << 16);
wrmsr(MDD_LEG_IO, msr); wrmsr(MDD_LEG_IO, msr);
@ -330,19 +340,17 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
/* COM2 */ /* COM2 */
if (sb->com2_enable) { if (sb->com2_enable) {
printk(BIOS_SPEW, "uarts_init: enable COM2\n");
switch (sb->com2_address) { switch (sb->com2_address) {
case 0x3F8: case 0x3F8:
addr = 7; addr = 7;
break; break;
case 0x3E8: case 0x3E8:
addr = 6; addr = 6;
break; break;
case 0x2F8: case 0x2F8:
addr = 5; addr = 5;
break; break;
case 0x2E8: case 0x2E8:
addr = 4; addr = 4;
break; break;
@ -350,11 +358,13 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
msr = rdmsr(MDD_LEG_IO); msr = rdmsr(MDD_LEG_IO);
msr.lo |= addr << 20; msr.lo |= addr << 20;
wrmsr(MDD_LEG_IO, msr); wrmsr(MDD_LEG_IO, msr);
printk(BIOS_SPEW, "uarts_init: wrote COM2 address 0x%x\n", sb->com2_address);
/* Set the IRQ */ /* Set the IRQ. */
msr = rdmsr(MDD_IRQM_YHIGH); msr = rdmsr(MDD_IRQM_YHIGH);
msr.lo |= sb->com2_irq << 28; msr.lo |= sb->com2_irq << 28;
wrmsr(MDD_IRQM_YHIGH, msr); wrmsr(MDD_IRQM_YHIGH, msr);
printk(BIOS_SPEW, "uarts_init: set COM2 irq\n");
/* GPIO3 - UART2_RX */ /* GPIO3 - UART2_RX */
/* Set: Input Enable (0x20) */ /* Set: Input Enable (0x20) */
@ -365,34 +375,42 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
/* GPIO4 - UART2_TX */ /* GPIO4 - UART2_TX */
/* Set: Output Enable (0x4) */ /* Set: Output Enable (0x4) */
outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
printk(BIOS_SPEW, "uarts_init: set output enable\n");
/* Set: OUTAUX1 Select (0x10) */ /* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");
/* Set: GPIO 3 and 4 Pull Up (0x18) */ /* Set: GPIO 3 + 4 Pull Up (0x18) */
outl(GPIOL_3_SET | GPIOL_4_SET, outl(GPIOL_3_SET | GPIOL_4_SET,
gpio_addr + GPIOL_PULLUP_ENABLE); gpio_addr + GPIOL_PULLUP_ENABLE);
printk(BIOS_SPEW, "uarts_init: set pullup COM2\n");
/* enable COM2 */ /* Enable COM2.
/* Bit 1 = device enable Bit 4 = allow access to the upper banks */ *
* Bit 1 = device enable
* Bit 4 = allow access to the upper banks
*/
msr.lo = (1 << 4) | (1 << 1); msr.lo = (1 << 4) | (1 << 1);
msr.hi = 0; msr.hi = 0;
wrmsr(MDD_UART2_CONF, msr); wrmsr(MDD_UART2_CONF, msr);
printk(BIOS_SPEW, "uarts_init: COM2 enabled\n");
} else { } else {
/* Reset and disable COM2 */ printk(BIOS_SPEW, "uarts_init: disable COM2\n");
/* Reset and disable COM2. */
msr = rdmsr(MDD_UART2_CONF); msr = rdmsr(MDD_UART2_CONF);
msr.lo = 1; // reset msr.lo = 1; /* Reset */
wrmsr(MDD_UART2_CONF, msr); wrmsr(MDD_UART2_CONF, msr);
msr.lo = 0; // disabled msr.lo = 0; /* Disabled */
wrmsr(MDD_UART2_CONF, msr); wrmsr(MDD_UART2_CONF, msr);
/* Disable the IRQ */ /* Disable the IRQ. */
msr = rdmsr(MDD_LEG_IO); msr = rdmsr(MDD_LEG_IO);
msr.lo &= ~(0xF << 20); msr.lo &= ~(0xF << 20);
wrmsr(MDD_LEG_IO, msr); wrmsr(MDD_LEG_IO, msr);
} }
} }
#define HCCPARAMS 0x08 #define HCCPARAMS 0x08
#define IPREG04 0xA0 #define IPREG04 0xA0
#define USB_HCCPW_SET (1 << 1) #define USB_HCCPW_SET (1 << 1)

75
src/southbridge/amd/cs5536/cs5536_early_setup.c
View File

@ -153,47 +153,98 @@ static void cs5536_setup_cis_mode(void)
wrmsr(GLPCI_SB_CTRL, msr); wrmsr(GLPCI_SB_CTRL, msr);
} }
/* see page 412 of the cs5536 companion book */ /**
static void cs5536_setup_onchipuart(void) * Enable the on-chip UART.
*
* See page 412 of the AMD Geode CS5536 Companion Device data book.
*/
void cs5536_setup_onchipuart1(void)
{ {
msr_t msr; msr_t msr;
/* Setup early for polling only mode. /* Setup early for polling only mode.
* 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1 * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
* GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
* 2. Enable UART IO space in MDD * 2. Enable UART I/O space in MDD.
* MSR 0x51400014 bit 18:16 * MSR 0x51400014 bit 18:16
* 3. Enable UART controller * 3. Enable UART controller.
* MSR 0x5140003A bit 0, 1 * MSR 0x5140003A bit 0, 1
*/ */
/* GPIO8 - UART1_TX */ /* GPIO8 - UART1_TX */
/* Set: Output Enable (0x4) */ /* Set: Output Enable (0x4) */
outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */ /* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
/* GPIO9 - UART1_RX */ /* GPIO9 - UART1_RX */
/* Set: Input Enable (0x20) */ /* Set: Input Enable (0x20) */
outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
/* Set: INAUX1 Select (0x34) */ /* Set: INAUX1 Select (0x34) */
outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
/* set address to 3F8 */ /* Set address to 0x3F8. */
msr = rdmsr(MDD_LEG_IO); msr = rdmsr(MDD_LEG_IO);
msr.lo |= 0x7 << 16; msr.lo |= 0x7 << 16;
wrmsr(MDD_LEG_IO, msr); wrmsr(MDD_LEG_IO, msr);
/* Bit 1 = DEVEN (device enable) /* Bit 1 = DEVEN (device enable)
* Bit 4 = EN_BANKS (allow access to the upper banks * Bit 4 = EN_BANKS (allow access to the upper banks)
*/ */
msr.lo = (1 << 4) | (1 << 1); msr.lo = (1 << 4) | (1 << 1);
msr.hi = 0; msr.hi = 0;
/* enable COM1 */ /* Enable COM1. */
wrmsr(MDD_UART1_CONF, msr); wrmsr(MDD_UART1_CONF, msr);
} }
void cs5536_setup_onchipuart2(void)
{
msr_t msr;
/* GPIO4 - UART2_TX */
/* Set: Output Enable (0x4) */
outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
/* GPIO4 - UART2_RX */
/* Set: Input Enable (0x20) */
outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
/* Set: INAUX1 Select (0x34) */
outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
/* Set: GPIO 3 + 3 Pull Up (0x18) */
outl(GPIOL_3_SET | GPIOL_4_SET,
GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
/* set address to 2F8 */
msr = rdmsr(MDD_LEG_IO);
msr.lo |= 0x5 << 20;
wrmsr(MDD_LEG_IO, msr);
/* Bit 1 = DEVEN (device enable)
* Bit 4 = EN_BANKS (allow access to the upper banks
*/
msr.lo = (1 << 4) | (1 << 1);
msr.hi = 0;
/* enable COM2 */
wrmsr(MDD_UART2_CONF, msr);
}
void cs5536_setup_onchipuart(int uart)
{
switch (uart) {
case 1:
cs5536_setup_onchipuart1();
break;
case 2:
cs5536_setup_onchipuart2();
break;
}
}
/* note: you can't do prints in here in most cases, /* note: you can't do prints in here in most cases,
* and we don't want to hang on serial, so they are * and we don't want to hang on serial, so they are
* commented out * commented out