mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK
Warning: not tested on hardware. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38867 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,14 +13,10 @@
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# GNU General Public License for more details.
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#
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config BOARD_AMD_OLIVEHILL
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def_bool n
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if BOARD_AMD_OLIVEHILL
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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#select ROMCC_BOOTBLOCK
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select CPU_AMD_AGESA_FAMILY16_KB
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select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
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select SOUTHBRIDGE_AMD_AGESA_YANGTZE
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@ -1,2 +1,2 @@
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#config BOARD_AMD_OLIVEHILL
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# bool"Olive Hill"
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config BOARD_AMD_OLIVEHILL
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bool "Olive Hill"
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@ -13,6 +13,8 @@
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# GNU General Public License for more details.
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#
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bootblock-y += bootblock.c
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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@ -1,8 +1,6 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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@ -13,32 +11,17 @@
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <amdblocks/acpimmio.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <southbridge/amd/agesa/hudson/hudson.h>
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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void board_BeforeAgesa(struct sysinfo *cb)
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void bootblock_mainboard_early_init(void)
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{
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int i;
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u32 val;
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/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
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* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
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* even though the register is not documented in the Kabini BKDG.
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* Otherwise the serial output is bad code.
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*/
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pm_io_write8(0xd2, 0);
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/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
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pm_io_write8(0xea, 1);
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/* Set LPC decode enables. */
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pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
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pci_write_config32(dev, 0x44, 0xff03ffd5);
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pm_write8(0xea, 0x1);
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/* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
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for (i = 0; i < 200000; i++)
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