skylake: ACPI: Clean up and fix XHCI ACPI Device
- Remove the old workarounds for XHCI from broadwell - Add PMC device to expose bits needed for XHCI workarounds - Implement the new workarounds for XHCI, the first will set a bit in the XHCI MMIO and the second will send a message to the PMC if a bit is set indicating the workaround is available. - Clean up the HS/SS port defines and remove unnecessary methods to determine the port count since we only support SPT-LP. BUG=chrome-os-partner:44622,chrome-os-partner:44518 BRANCH=none TEST=build and boot on glados, verify that D0 and D3 can be made to work (by disabling unused USB and the misbehaving camera) Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88 Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295950 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11537 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
Patrick Georgi
parent
bf31983836
commit
e32da955b3
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@ -40,6 +40,9 @@
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/* PCR Access */
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#include "pcr.asl"
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/* PMC 0:1f.2 */
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#include "pmc.asl"
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/* Serial IO */
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#include "serialio.asl"
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@ -0,0 +1,45 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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Device (PMC)
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{
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Name (_ADR, 0x001f0002)
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Name (_DDN, "Power Management Controller")
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OperationRegion (PMCP, PCI_Config, 0x00, 0x100)
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Field (PMCP, AnyAcc, NoLock, Preserve)
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{
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Offset (0x48),
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, 12,
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PWRM, 20, /* PWRMBASE */
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}
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OperationRegion (PMCM, SystemMemory, ShiftLeft (PWRM, 12), 0x3f)
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Field (PMCM, DWordAcc, NoLock, Preserve)
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{
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Offset (0x1c), /* PCH_PM_STS */
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, 24,
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PMFS, 1, /* PMC_MSG_FULL_STS */
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Offset (0x20),
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MPMC, 32, /* MTPMC */
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Offset (0x24), /* PCH_PM_STS2 */
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, 20,
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UWAB, 1, /* USB2 Workaround Available */
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}
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}
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -25,297 +25,162 @@ Device (XHCI)
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{
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Name (_ADR, 0x00140000)
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Name (PLSD, 5) /* Port Link State - RxDetect */
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Name (PLSP, 7) /* Port Link State - Polling */
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Name (_PRW, Package () { GPE0_PME_B0, 3 })
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Method (_DSW, 3)
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{
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Store (Arg0, PMEE)
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}
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Name (_S3D, 3) /* D3 supported in S3 */
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Name (_S4D, 3) /* D3 supported in S4 */
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Name (_S0W, 3) /* D3 can wake device in S0 */
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Name (_S3W, 3) /* D3 can wake system from S3 */
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Name (_S4W, 3) /* D3 can wake system from S4 */
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OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
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Field (XPRT, AnyAcc, NoLock, Preserve)
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{
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Offset (0x0),
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DVID, 16,
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DVID, 16, /* VENDORID */
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Offset (0x10),
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, 16,
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XMEM, 16, /* MEM_BASE */
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Offset (0x74),
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D0D3, 2,
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D0D3, 2, /* POWERSTATE */
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, 6,
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PMEE, 1, /* PME_EN */
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, 6,
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PMES, 1, /* PME_STS */
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Offset (0xA8),
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, 13,
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MW13, 1,
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MW14, 1,
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, 17,
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Offset (0xb0),
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, 13,
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MB13, 1,
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MB14, 1,
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, 17,
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Offset (0xd0),
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PR2, 32, /* USB2PR */
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PR2M, 32, /* USB2PRM */
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PR3, 32, /* USB3PR */
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PR3M, 32, /* USB3PRM */
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}
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Method (USRA,0){
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Return(11)
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}
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Method (SSPA,0){
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Return (13)
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}
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/* Clear status bits */
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Method (LPCL, 0, Serialized)
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{
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OperationRegion (XREG, SystemMemory,
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ShiftLeft (^XMEM, 16), 0x600)
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Add (ShiftLeft (XMEM, 16), 0x8000), 0x200)
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Field (XREG, DWordAcc, Lock, Preserve)
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{
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Offset (0x510), /* PORTSCNUSB3[0]*/
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PSC0, 32,
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Offset (0x520), /* PORTSCNUSB3[1]*/
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PSC1, 32,
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Offset (0x530), /* PORTSCNUSB3[2]*/
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PSC2, 32,
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Offset (0x540), /* PORTSCNUSB3[3]*/
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PSC3, 32,
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Offset (0x1c4), /* USB2PMCTRL */
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, 2,
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UPSW, 2, /* U2PSUSPGP */
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}
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/* Port Enabled/Disabled (Bit 1)*/
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Name (PEDB, ShiftLeft (1, 1))
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/* Change Status (Bits 23:17)*/
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Name (CHST, ShiftLeft (0x7f, 17))
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/* Port 0 */
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And (PSC0, Not (PEDB), Local0)
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Or (Local0, CHST, PSC0)
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/* Port 1 */
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And (PSC1, Not (PEDB), Local0)
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Or (Local0, CHST, PSC1)
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/* Port 2 */
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And (PSC2, Not (PEDB), Local0)
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Or (Local0, CHST, PSC2)
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/* Port 3 */
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And (PSC3, Not (PEDB), Local0)
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Or (Local0, CHST, PSC3)
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}
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Method (LPS0, 0, Serialized)
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{
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OperationRegion (XREG, SystemMemory,
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ShiftLeft (^XMEM, 16), 0x600)
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Field (XREG, DWordAcc, Lock, Preserve)
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{
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Offset (0x510), // PORTSCNUSB3
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, 5,
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PLS1, 4, // [8:5] Port Link State
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PPR1, 1, // [9] Port Power
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, 7,
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CSC1, 1, // [17] Connect Status Change
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, 1,
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WRC1, 1, // [19] Warm Port Reset Change
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, 11,
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WPR1, 1, // [31] Warm Port Reset
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Offset (0x520), // PORTSCNUSB3
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, 5,
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PLS2, 4, // [8:5] Port Link State
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PPR2, 1, // [9] Port Power
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, 7,
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CSC2, 1, // [17] Connect Status Change
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, 1,
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WRC2, 1, // [19] Warm Port Reset Change
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, 11,
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WPR2, 1, // [31] Warm Port Reset
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Offset (0x530), // PORTSCNUSB3
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, 5,
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PLS3, 4, // [8:5] Port Link State
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PPR3, 1, // [9] Port Power
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, 7,
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CSC3, 1, // [17] Connect Status Change
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, 1,
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WRC3, 1, // [19] Warm Port Reset Change
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, 11,
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WPR3, 1, // [31] Warm Port Reset
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Offset (0x540), // PORTSCNUSB3
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, 5,
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PLS4, 4, // [8:5] Port Link State
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PPR4, 1, // [9] Port Power
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, 7,
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CSC4, 1, // [17] Connect Status Change
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, 1,
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WRC4, 1, // [19] Warm Port Reset Change
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, 11,
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WPR4, 1, // [31] Warm Port Reset
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}
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/* Wait for all powered ports to finish polling*/
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Store (10, Local0)
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While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)),
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LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))),
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LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)),
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LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP)))))
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{
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If (LEqual (Local0, 0)) {
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Break
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}
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Decrement (Local0)
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Stall (10)
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}
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/* For each USB3 Port:*/
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/* If port is disconnected (PLS=5 PP=1 CSC=0)*/
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/* 1) Issue warm reset (WPR=1)*/
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/* 2) Poll for warm reset complete (WRC=0)*/
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/* 3) Write 1 to port status to clear*/
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/* Local# indicate if port is reset*/
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Store (0, Local1)
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Store (0, Local2)
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Store (0, Local3)
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Store (0, Local4)
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If (LAnd (LEqual (PLS1, PLSD),
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LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) {
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Store (1, WPR1) /* Issue warm reset*/
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Store (1, Local1)
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}
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If (LAnd (LEqual (PLS2, PLSD),
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LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) {
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Store (1, WPR2) /* Issue warm reset*/
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Store (1, Local2)
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}
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If (LAnd (LEqual (PLS3, PLSD),
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LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) {
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Store (1, WPR3) /* Issue warm reset*/
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Store (1, Local3)
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}
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If (LAnd (LEqual (PLS4, PLSD),
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LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) {
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Store (1, WPR4) /* Issue warm reset*/
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Store (1, Local4)
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}
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/* Poll for warm reset complete on all ports that were reset*/
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Store (10, Local0)
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While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)),
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LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))),
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LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)),
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LAnd (LEqual (Local4, 1), LEqual (WRC4, 0)))))
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{
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If (LEqual (Local0, 0)) {
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Break
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}
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Decrement (Local0)
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Stall (10)
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}
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/* Clear status bits in all ports */
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LPCL ()
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}
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Method (_PSC, 0, NotSerialized)
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Method (_PSC, 0, Serialized)
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{
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Return (^D0D3)
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}
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Method (_PS0, 0, Serialized)
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{
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If (LEqual (^DVID, 0xFFFF)) {
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Return
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}
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If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
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Return
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}
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/* If device is in D3, set back to D0 */
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If (LEqual (^D0D3, 3)) {
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Store (Zero, ^D0D3)
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Store (^D0D3, Local0)
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}
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/* Disable USB2 PHY SUS Well Power Gating */
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Store (Zero, ^UPSW)
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/*
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* Apply USB2 PHPY Power Gating workaround if needed.
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*/
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If (^^PMC.UWAB) {
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/* Write to MTPMC to have PMC disable power gating */
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Store (1, ^^PMC.MPMC)
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/* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */
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Store (10, Local0)
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While (^^PMC.PMFS) {
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If (LNot (Local0)) {
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Break
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}
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Decrement (Local0)
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Sleep (10)
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}
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}
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}
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Method (_PS3, 0, Serialized)
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{
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If (LEqual (^DVID, 0xFFFF)) {
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Return
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}
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If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
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Return
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}
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Name (_PRW, Package(){ 0x6d, 3 })
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/* Clear PME Status */
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Store (1, ^PMES)
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/* Leave USB ports on for to allow Wake from USB */
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/* Enable PME */
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Store (1, ^PMEE)
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Method (_S3D,0) /* Highest D State in S3 State*/
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{
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Return (3)
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/* If device is in D3, set back to D0 */
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If (LEqual (^D0D3, 3)) {
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Store (Zero, ^D0D3)
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Store (^D0D3, Local0)
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}
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Method (_S4D,0) /* Highest D State in S4 State*/
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{
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Return (3)
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/* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */
|
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Store (3, ^UPSW)
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|
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/* Now put device in D3 */
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Store (3, ^D0D3)
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Store (^D0D3, Local0)
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/*
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* Apply USB2 PHPY Power Gating workaround if needed.
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* This code assumes XDCI is disabled, if it is enabled
|
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* then this must also check if it is in D3 state too.
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*/
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If (^^PMC.UWAB) {
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/* Write to MTPMC to have PMC enable power gating */
|
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Store (3, ^^PMC.MPMC)
|
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|
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/* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */
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Store (10, Local0)
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While (^^PMC.PMFS) {
|
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If (LNot (Local0)) {
|
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Break
|
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}
|
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Device (HS01)
|
||||
{
|
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Name(_ADR, 0x01)
|
||||
Decrement (Local0)
|
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Sleep (10)
|
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}
|
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Device (HS02)
|
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{
|
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Name(_ADR, 0x02)
|
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}
|
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Device (HS03)
|
||||
{
|
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Name(_ADR, 0x03)
|
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}
|
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Device (HS04)
|
||||
{
|
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Name(_ADR, 0x04)
|
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}
|
||||
Device (HS05)
|
||||
{
|
||||
Name(_ADR, 0x05)
|
||||
}
|
||||
Device (HS06)
|
||||
{
|
||||
Name(_ADR, 0x06)
|
||||
}
|
||||
Device (HS07)
|
||||
{
|
||||
Name(_ADR, 0x07)
|
||||
}
|
||||
Device (HS08)
|
||||
{
|
||||
Name(_ADR, 0x08)
|
||||
}
|
||||
Device (HS09)
|
||||
{
|
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Name(_ADR, 0x09)
|
||||
}
|
||||
Device (HS10)
|
||||
{
|
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Name(_ADR, 0x10)
|
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}
|
||||
Device (USR1)
|
||||
{
|
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Method(_ADR) { Return (Add(USRA(),0)) }
|
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}
|
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Device (USR2)
|
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{
|
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Method(_ADR) { Return (Add(USRA(),1)) }
|
||||
}
|
||||
Device (SS01)
|
||||
{
|
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Method(_ADR) { Return (Add(SSPA(),0)) }
|
||||
}
|
||||
Device (SS02)
|
||||
{
|
||||
Method(_ADR) { Return (Add(SSPA(),1)) }
|
||||
}
|
||||
Device (SS03)
|
||||
{
|
||||
Method(_ADR) { Return (Add(SSPA(),2)) }
|
||||
}
|
||||
Device (SS04)
|
||||
{
|
||||
Method(_ADR) { Return (Add(SSPA(),3)) }
|
||||
}
|
||||
Device (SS05)
|
||||
{
|
||||
Method(_ADR) { Return (Add(SSPA(),4)) }
|
||||
}
|
||||
Device (SS06)
|
||||
{
|
||||
Method(_ADR) { Return (Add(SSPA(),5)) }
|
||||
}
|
||||
}
|
||||
|
||||
/* Root Hub for Skylake-LP PCH */
|
||||
Device (RHUB)
|
||||
{
|
||||
Name (_ADR, Zero)
|
||||
|
||||
/* USB2 */
|
||||
Device (HS01) { Name (_ADR, 1) }
|
||||
Device (HS02) { Name (_ADR, 2) }
|
||||
Device (HS03) { Name (_ADR, 3) }
|
||||
Device (HS04) { Name (_ADR, 4) }
|
||||
Device (HS05) { Name (_ADR, 5) }
|
||||
Device (HS06) { Name (_ADR, 6) }
|
||||
Device (HS07) { Name (_ADR, 7) }
|
||||
Device (HS08) { Name (_ADR, 8) }
|
||||
Device (HS09) { Name (_ADR, 9) }
|
||||
Device (HS10) { Name (_ADR, 10) }
|
||||
|
||||
/* USBr */
|
||||
Device (USR1) { Name (_ADR, 11) }
|
||||
Device (USR2) { Name (_ADR, 12) }
|
||||
|
||||
/* USB3 */
|
||||
Device (SS01) { Name (_ADR, 13) }
|
||||
Device (SS02) { Name (_ADR, 14) }
|
||||
Device (SS03) { Name (_ADR, 15) }
|
||||
Device (SS04) { Name (_ADR, 16) }
|
||||
Device (SS05) { Name (_ADR, 17) }
|
||||
Device (SS06) { Name (_ADR, 18) }
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue