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soc/intel/skylake: Refactor PEG configuration 

Simplify some if-blocks which are used for the configuration, enablement
and disablement of the PEG devices.

This changes the logic of the code, since it configures PegxEnable
before the if-blocks, where x is the number of the PEG device, and the
further configuration of the PEG devices depends on the enablement of
PegxEnable.

Change-Id: I6dd88ce752ce8f0255c424d0e5b2d8ef918885a1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-08-11 06:57:44 +02:00 committed by Michael Niewöhner
parent 736de9f246
commit e32fa4e152
1 changed files with 6 additions and 12 deletions
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18
src/soc/intel/skylake/romstage/romstage.c
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@ -171,10 +171,8 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
* in FSP * in FSP
*/ */
dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
if (!dev || !dev->enabled) m_cfg->Peg0Enable = dev && dev->enabled;
m_cfg->Peg0Enable = 0; if (m_cfg->Peg0Enable) {
else if (dev->enabled) {
m_cfg->Peg0Enable = dev->enabled;
m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
/* Use maximum possible link speed */ /* Use maximum possible link speed */
m_cfg->Peg0MaxLinkSpeed = 0; m_cfg->Peg0MaxLinkSpeed = 0;
@ -186,10 +184,8 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
} }
dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
if (!dev || !dev->enabled) m_cfg->Peg1Enable = dev && dev->enabled;
m_cfg->Peg1Enable = 0; if (m_cfg->Peg1Enable) {
else if (dev->enabled) {
m_cfg->Peg1Enable = dev->enabled;
m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
m_cfg->Peg1MaxLinkSpeed = 0; m_cfg->Peg1MaxLinkSpeed = 0;
m_cfg->Peg1PowerDownUnusedLanes = 1; m_cfg->Peg1PowerDownUnusedLanes = 1;
@ -198,10 +194,8 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
} }
dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
if (!dev || !dev->enabled) m_cfg->Peg2Enable = dev && dev->enabled;
m_cfg->Peg2Enable = 0; if (m_cfg->Peg2Enable) {
else if (dev->enabled) {
m_cfg->Peg2Enable = dev->enabled;
m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
m_cfg->Peg2MaxLinkSpeed = 0; m_cfg->Peg2MaxLinkSpeed = 0;
m_cfg->Peg2PowerDownUnusedLanes = 1; m_cfg->Peg2PowerDownUnusedLanes = 1;