skylake: fix serial port with new code base
Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.
Note: It's still a requirement to manually unset the
8250IO option because that's unconditionally set.
BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.
Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11172
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
parent
14bb36c5ca
commit
e33a1724b3
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@ -188,12 +188,16 @@ config SMM_TSEG_SIZE
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hex
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default 0x800000
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config TTYS0_BASE
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hex
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default 0xfe034000
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config VGA_BIOS_ID
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string
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default "8086,0406"
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config UART_DEBUG
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bool "Enable UART debug port."
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default y if CONSOLE_SERIAL
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default n
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select DRIVERS_UART
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select DRIVERS_UART_8250MEM
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select DRIVERS_UART_8250MEM_32
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endif
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@ -19,6 +19,7 @@ romstage-y += pei_data.c
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romstage-y += pmutil.c
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romstage-y += smbus_common.c
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romstage-y += tsc_freq.c
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romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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@ -46,6 +47,7 @@ ramstage-y += smmrelocate.c
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ramstage-y += systemagent.c
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ramstage-y += tsc_freq.c
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ramstage-y += uart.c
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ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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ramstage-y += xhci.c
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smm-y += cpu_info.c
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@ -57,6 +59,7 @@ smm-y += pmutil.c
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smm-y += smihandler.c
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smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_UART_DEBUG) += uart_debug.c
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CPPFLAGS_common += -I$(src)/arch/x86/include/
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CPPFLAGS_common += -I$(src)/soc/intel/skylake
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@ -27,6 +27,9 @@
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#define PCH_PCR_BASE_ADDRESS 0xfd000000
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#define PCH_BCR_BASE_SIZE 0x1000000
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#define UART_DEBUG_BASE_ADDRESS 0xfe034000
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#define UART_DEBUG_BASE_SIZE 0x1000
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#define MCH_BASE_ADDRESS 0xfed10000
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#define MCH_BASE_SIZE 0x8000
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@ -50,7 +50,7 @@ void soc_pre_console_init(struct romstage_params *params)
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/* System Agent Early Initialization */
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systemagent_early_init();
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if (IS_ENABLED(CONFIG_CONSOLE_UART8250MEM_32))
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if (IS_ENABLED(CONFIG_UART_DEBUG))
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pch_uart_init();
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}
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@ -19,6 +19,7 @@
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*/
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#include <arch/io.h>
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#include <console/uart.h>
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#include <device/pci_def.h>
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#include <stdint.h>
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#include <soc/pci_devs.h>
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@ -33,7 +34,7 @@ void pch_uart_init(void)
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{
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device_t dev = PCH_DEV_UART2;
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u32 tmp;
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u8 *base = (u8 *)CONFIG_TTYS0_BASE;
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u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE);
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/* Set configured UART2 base address */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
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@ -49,7 +50,11 @@ void pch_uart_init(void)
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SIO_REG_PPR_RESETS_IDMA;
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write32(base + SIO_REG_PPR_RESETS, tmp);
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/* Set M and N divisor inputs and enable clock */
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/*
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* Set M and N divisor inputs and enable clock.
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* Main reference frequency to UART is:
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* 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
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*/
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tmp = read32(base + SIO_REG_PPR_CLOCK);
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tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
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(SIO_REG_PPR_CLOCK_N_DIV << 16) |
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@ -57,7 +62,7 @@ void pch_uart_init(void)
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write32(base + SIO_REG_PPR_CLOCK, tmp);
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/* Put UART2 in byte access mode for 16550 compatibility */
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if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32))
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if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
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pcr_andthenor32(PID_SERIALIO,
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R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2);
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@ -18,11 +18,11 @@
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* Foundation, Inc.
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*/
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#include <console/uart.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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@ -36,10 +36,11 @@ static void pch_uart_read_resources(struct device *dev)
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pci_dev_read_resources(dev);
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/* Set the configured UART base address for the debug port */
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if (IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32) &&
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pch_uart_is_debug(dev)) {
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if (IS_ENABLED(CONFIG_UART_DEBUG) && pch_uart_is_debug(dev)) {
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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res->size = 0x1000;
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/* Need to set the base and size for the resource allocator. */
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res->base = UART_DEBUG_BASE_ADDRESS;
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res->size = UART_DEBUG_BASE_SIZE;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED;
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}
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@ -0,0 +1,41 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <stddef.h>
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#include <console/uart.h>
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#include <soc/iomap.h>
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#include <soc/serialio.h>
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unsigned int uart_platform_refclk(void)
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{
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/*
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* Set M and N divisor inputs and enable clock.
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* Main reference frequency to UART is:
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* 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
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* The different order below is to handle integer math overflow.
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*/
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return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV;
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}
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uintptr_t uart_platform_base(int idx)
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{
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/* Same base address for all debug port usage. In reality UART2
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* is currently only supported. */
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return UART_DEBUG_BASE_ADDRESS;
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}
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