cpu/amd/{agesa,pi}: Select NO_FIXED_XIP_ROM_SIZE
AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol. Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -28,20 +28,10 @@ config CPU_AMD_AGESA
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select LAPIC_MONOTONIC_TIMER
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select LAPIC_MONOTONIC_TIMER
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select SPI_FLASH if HAVE_ACPI_RESUME
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select SPI_FLASH if HAVE_ACPI_RESUME
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select SMM_ASEG
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select SMM_ASEG
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select NO_FIXED_XIP_ROM_SIZE
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if CPU_AMD_AGESA
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if CPU_AMD_AGESA
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config XIP_ROM_SIZE
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hex
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default 0x100000
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help
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Overwride the default write through caching size as 1M Bytes.
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On some AMD platforms, one socket supports 2 or more kinds of
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processor family, compiling several CPU families agesa code
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will increase the romstage size.
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In order to execute romstage in place on the flash ROM,
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more space is required to be set as write through caching.
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config UDELAY_LAPIC_FIXED_FSB
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config UDELAY_LAPIC_FIXED_FSB
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int
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int
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default 200
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default 200
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@ -21,8 +21,4 @@ config CPU_ADDR_BITS
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int
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int
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default 48
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default 48
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config XIP_ROM_SIZE
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hex
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default 0x80000
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endif
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endif
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@ -21,8 +21,4 @@ config CPU_ADDR_BITS
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int
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int
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default 36
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default 36
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config XIP_ROM_SIZE
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hex
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default 0x80000
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endif
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endif
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@ -21,8 +21,4 @@ config CPU_ADDR_BITS
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int
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int
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default 48
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default 48
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config XIP_ROM_SIZE
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hex
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default 0x100000
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endif
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endif
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@ -21,10 +21,6 @@ config CPU_ADDR_BITS
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int
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int
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default 40
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default 40
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config XIP_ROM_SIZE
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hex
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default 0x100000
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config FORCE_AM1_SOCKET_SUPPORT
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config FORCE_AM1_SOCKET_SUPPORT
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bool
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bool
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default n
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default n
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@ -21,8 +21,4 @@ config CPU_ADDR_BITS
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int
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int
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default 48
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default 48
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config XIP_ROM_SIZE
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hex
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default 0x100000
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endif
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endif
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@ -21,8 +21,4 @@ config CPU_ADDR_BITS
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int
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int
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default 48
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default 48
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config XIP_ROM_SIZE
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hex
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default 0x100000
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endif
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endif
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@ -23,8 +23,4 @@ config CPU_ADDR_BITS
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int
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int
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default 40
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default 40
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config XIP_ROM_SIZE
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hex
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default 0x100000
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endif
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endif
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@ -28,23 +28,13 @@ config CPU_AMD_PI
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select SPI_FLASH if HAVE_ACPI_RESUME
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select SPI_FLASH if HAVE_ACPI_RESUME
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select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
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select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
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select SMM_ASEG
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select SMM_ASEG
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select NO_FIXED_XIP_ROM_SIZE
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if CPU_AMD_PI
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if CPU_AMD_PI
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config BINARYPI_LEGACY_WRAPPER
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config BINARYPI_LEGACY_WRAPPER
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def_bool n
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def_bool n
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config XIP_ROM_SIZE
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hex
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default 0x100000
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help
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Overwride the default write through caching size as 1M Bytes.
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On some AMD platforms, one socket supports 2 or more kinds of
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processor family, compiling several CPU families agesa code
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will increase the romstage size.
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In order to execute romstage in place on the flash ROM,
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more space is required to be set as write through caching.
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config UDELAY_LAPIC_FIXED_FSB
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config UDELAY_LAPIC_FIXED_FSB
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int
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int
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default 200
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default 200
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