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cpu/amd/{agesa,pi}: Select NO_FIXED_XIP_ROM_SIZE 

AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the
romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol.

Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Arthur Heymans 2019-10-06 17:39:44 +02:00 committed by Patrick Georgi
parent e9649218bf
commit e33c50d74c
9 changed files with 2 additions and 50 deletions
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12
src/cpu/amd/agesa/Kconfig
View File

@ -28,20 +28,10 @@ config CPU_AMD_AGESA
select LAPIC_MONOTONIC_TIMER select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME select SPI_FLASH if HAVE_ACPI_RESUME
select SMM_ASEG select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE
if CPU_AMD_AGESA if CPU_AMD_AGESA
config XIP_ROM_SIZE
hex
default 0x100000
help
Overwride the default write through caching size as 1M Bytes.
On some AMD platforms, one socket supports 2 or more kinds of
processor family, compiling several CPU families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.
config UDELAY_LAPIC_FIXED_FSB config UDELAY_LAPIC_FIXED_FSB
int int
default 200 default 200

4
src/cpu/amd/agesa/family12/Kconfig
View File

@ -21,8 +21,4 @@ config CPU_ADDR_BITS
int int
default 48 default 48
config XIP_ROM_SIZE
hex
default 0x80000
endif endif

4
src/cpu/amd/agesa/family14/Kconfig
View File

@ -21,8 +21,4 @@ config CPU_ADDR_BITS
int int
default 36 default 36
config XIP_ROM_SIZE
hex
default 0x80000
endif endif

4
src/cpu/amd/agesa/family15tn/Kconfig
View File

@ -21,8 +21,4 @@ config CPU_ADDR_BITS
int int
default 48 default 48
config XIP_ROM_SIZE
hex
default 0x100000
endif endif

4
src/cpu/amd/agesa/family16kb/Kconfig
View File

@ -21,10 +21,6 @@ config CPU_ADDR_BITS
int int
default 40 default 40
config XIP_ROM_SIZE
hex
default 0x100000
config FORCE_AM1_SOCKET_SUPPORT config FORCE_AM1_SOCKET_SUPPORT
bool bool
default n default n

4
src/cpu/amd/pi/00630F01/Kconfig
View File

@ -21,8 +21,4 @@ config CPU_ADDR_BITS
int int
default 48 default 48
config XIP_ROM_SIZE
hex
default 0x100000
endif endif

4
src/cpu/amd/pi/00660F01/Kconfig
View File

@ -21,8 +21,4 @@ config CPU_ADDR_BITS
int int
default 48 default 48
config XIP_ROM_SIZE
hex
default 0x100000
endif endif

4
src/cpu/amd/pi/00730F01/Kconfig
View File

@ -23,8 +23,4 @@ config CPU_ADDR_BITS
int int
default 40 default 40
config XIP_ROM_SIZE
hex
default 0x100000
endif endif

12
src/cpu/amd/pi/Kconfig
View File

@ -28,23 +28,13 @@ config CPU_AMD_PI
select SPI_FLASH if HAVE_ACPI_RESUME select SPI_FLASH if HAVE_ACPI_RESUME
select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
select SMM_ASEG select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE
if CPU_AMD_PI if CPU_AMD_PI
config BINARYPI_LEGACY_WRAPPER config BINARYPI_LEGACY_WRAPPER
def_bool n def_bool n
config XIP_ROM_SIZE
hex
default 0x100000
help
Overwride the default write through caching size as 1M Bytes.
On some AMD platforms, one socket supports 2 or more kinds of
processor family, compiling several CPU families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.
config UDELAY_LAPIC_FIXED_FSB config UDELAY_LAPIC_FIXED_FSB
int int
default 200 default 200