mb/google/drallion: Add new mainboard
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake. BUG=b:138098572 Test=compiles Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Thejaswani Putta
Martin Roth
parent
efe7947ac2
commit
e3443d87cc
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@ -0,0 +1,106 @@
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config BOARD_GOOGLE_BASEBOARD_DRALLION
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_ISH
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select EC_GOOGLE_WILCO
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select GENERIC_SPD_BIN
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_TPM2
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select SOC_INTEL_COMETLAKE
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM2
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select MAINBOARD_USES_IFD_EC_REGION
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select MAINBOARD_USES_IFD_GBE_REGION
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select USE_SAR
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select SAR_ENABLE
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if BOARD_GOOGLE_BASEBOARD_DRALLION
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config CHROMEOS
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bool
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default y
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config DRIVER_TPM_I2C_BUS
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hex
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default 0x4
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config DRIVER_TPM_I2C_ADDR
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hex
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default 0x50
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 82 # GPE0_DW2_18 (GPP_D18)
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config POWER_OFF_ON_CR50_UPDATE
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bool
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default n
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config GBB_HWID
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string
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depends on CHROMEOS
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default "DRALLION TEST 3556"
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config MAINBOARD_DIR
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string
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default "google/drallion"
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config MAINBOARD_FAMILY
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string
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default "Google_Drallion"
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config MAINBOARD_PART_NUMBER
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string
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default "Drallion"
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config MAINBOARD_VENDOR
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string
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default "Google"
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config MAX_CPUS
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int
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default 8
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config UART_FOR_CONSOLE
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int
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default 2
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config VARIANT_DIR
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string
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default "drallion"
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config DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config VBOOT
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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select VBOOT_LID_SWITCH
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endif # BOARD_GOOGLE_BASEBOARD_DRALLION
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@ -0,0 +1,5 @@
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comment "Drallion"
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config BOARD_GOOGLE_DRALLION
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bool "-> Drallion"
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select BOARD_GOOGLE_BASEBOARD_DRALLION
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@ -0,0 +1,38 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2018 Google LLC
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += bootblock.c
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ramstage-y += ramstage.c
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ramstage-y += sku.c
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romstage-y += romstage.c
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smm-y += smihandler.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
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bootblock-y += ec.c
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ramstage-y += ec.c
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romstage-y += ec.c
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verstage-y += ec.c
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subdirs-y += variants/$(VARIANT_DIR)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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@ -0,0 +1,6 @@
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Vendor name: Google
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Board name: Drallion
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,34 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <ec/google/wilco/bootblock.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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static void early_config_gpio(void)
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{
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const struct pad_config *early_gpio_table;
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size_t num_gpios = 0;
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early_gpio_table = variant_early_gpio_table(&num_gpios);
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gpio_configure_pads(early_gpio_table, num_gpios);
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}
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void bootblock_mainboard_init(void)
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{
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early_config_gpio();
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wilco_ec_early_init();
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}
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@ -0,0 +1,127 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <variant/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <security/tpm/tss.h>
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#include <device/device.h>
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#include <intelblocks/pmclib.h>
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#include <soc/pmc.h>
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#include <soc/pci_devs.h>
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enum rec_mode_state {
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REC_MODE_UNINITIALIZED,
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REC_MODE_NOT_REQUESTED,
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REC_MODE_REQUESTED,
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};
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(),
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"write protect"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{-1, ACTIVE_HIGH, 0, "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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static int cros_get_gpio_value(int type)
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{
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const struct cros_gpio *cros_gpios;
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size_t i, num_gpios = 0;
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cros_gpios = variant_cros_gpios(&num_gpios);
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for (i = 0; i < num_gpios; i++) {
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const struct cros_gpio *gpio = &cros_gpios[i];
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if (gpio->type == type) {
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int state = gpio_get(gpio->gpio_num);
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if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
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return !state;
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else
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return state;
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}
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}
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return 0;
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *cros_gpios;
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size_t num_gpios = 0;
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cros_gpios = variant_cros_gpios(&num_gpios);
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chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
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}
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int get_write_protect_state(void)
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{
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return cros_get_gpio_value(CROS_GPIO_WP);
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}
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int get_recovery_mode_switch(void)
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{
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static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED;
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enum rec_mode_state state = REC_MODE_NOT_REQUESTED;
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uint8_t cr50_state = 0;
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/* Check cached state, since TPM will only tell us the first time */
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if (saved_rec_mode != REC_MODE_UNINITIALIZED)
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return saved_rec_mode == REC_MODE_REQUESTED;
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/*
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* Read one-time recovery request from cr50 in verstage only since
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* the TPM driver won't be set up in time for other stages like romstage
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* and the value from the TPM would be wrong anyway since the verstage
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* read would have cleared the value on the TPM.
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*
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* The TPM recovery request is passed between stages through the
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* vboot_get_shared_data or cbmem depending on stage.
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*/
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if (ENV_VERSTAGE &&
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tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS &&
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cr50_state)
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state = REC_MODE_REQUESTED;
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/* Read state from the GPIO controlled by servo. */
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if (cros_get_gpio_value(CROS_GPIO_REC))
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state = REC_MODE_REQUESTED;
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/* Store the state in case this is called again in verstage. */
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saved_rec_mode = state;
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return state == REC_MODE_REQUESTED;
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}
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int get_lid_switch(void)
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{
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return 1;
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}
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void mainboard_prepare_cr50_reset(void)
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{
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#if ENV_RAMSTAGE
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/* Ensure system powers up after CR50 reset */
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pmc_set_afterg3(MAINBOARD_POWER_STATE_ON);
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#endif
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}
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@ -0,0 +1,49 @@
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x400000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x100000
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SI_GBE(PRESERVE)@0x101000 0x2000
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SI_ME@0x103000 0x2f9000
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SI_PDR(PRESERVE)@0x3fc000 0x4000
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}
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SI_BIOS@0x400000 0x1c00000 {
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RW_DIAG@0x0 0x12d0000 {
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RW_LEGACY(CBFS)@0x0 0x12c0000
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DIAG_NVRAM@0x12c0000 0x10000
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}
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RW_SECTION_A@0x12d0000 0x280000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x26ffc0
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RW_FWID_A@0x27ffc0 0x40
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}
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RW_SECTION_B@0x1550000 0x280000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x26ffc0
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RW_FWID_B@0x27ffc0 0x40
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}
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RW_MISC@0x17d0000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG(PRESERVE)@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x28000 0x2000
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RW_NVRAM(PRESERVE)@0x2a000 0x6000
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}
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WP_RO@0x1800000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x3f0000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x300000
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}
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}
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}
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}
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@ -0,0 +1,81 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#include <variant/ec.h>
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, /* DSDT revision: ACPI v2.0 and up */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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)
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{
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/* Some generic macros */
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#include <soc/intel/cannonlake/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/cannonlake/acpi/globalnvs.asl>
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/* CPU */
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/cannonlake/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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}
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/* Per board variant mainboard hooks. */
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#include <variant/acpi/mainboard.asl>
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}
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#if CONFIG(CHROMEOS)
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* VPD support */
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#include <vendorcode/google/chromeos/acpi/vpd.asl>
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/* MAC address passthru */
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#include <vendorcode/google/chromeos/acpi/amac.asl>
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#endif
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/* Chipset specific sleep states */
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#include <soc/intel/cannonlake/acpi/sleepstates.asl>
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/* Low power idle table */
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#include <soc/intel/cannonlake/acpi/lpit.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/wilco/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/wilco/acpi/ec.asl>
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}
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include soc specific DPTF changes */
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#include <soc/intel/cannonlake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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}
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|
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@ -0,0 +1,23 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2019 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <ec/google/wilco/commands.h>
|
||||
#include <variant/ec.h>
|
||||
|
||||
void mainboard_post(uint8_t value)
|
||||
{
|
||||
wilco_ec_save_post_code(value);
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "variant/hda_verb.h"
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <boardid.h>
|
||||
#include <drivers/vpd/vpd.h>
|
||||
#include <smbios.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <variant/gpio.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
#define VPD_KEY_SYSTEM_SERIAL "serial_number"
|
||||
#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number"
|
||||
#define VPD_SERIAL_LEN 64
|
||||
|
||||
const char *smbios_system_serial_number(void)
|
||||
{
|
||||
static char serial[VPD_SERIAL_LEN];
|
||||
if (vpd_gets(VPD_KEY_SYSTEM_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO))
|
||||
return serial;
|
||||
return "";
|
||||
}
|
||||
|
||||
const char *smbios_mainboard_serial_number(void)
|
||||
{
|
||||
static char serial[VPD_SERIAL_LEN];
|
||||
if (vpd_gets(VPD_KEY_MAINBOARD_SERIAL, serial, VPD_SERIAL_LEN, VPD_RO))
|
||||
return serial;
|
||||
return "";
|
||||
}
|
||||
|
||||
/* mainboard silk screen shows DIMM-A and DIMM-B */
|
||||
void smbios_fill_dimm_locator(const struct dimm_info *dimm,
|
||||
struct smbios_type17 *t)
|
||||
{
|
||||
switch (dimm->channel_num) {
|
||||
case 0:
|
||||
t->device_locator = smbios_add_string(t->eos, "DIMM-A");
|
||||
break;
|
||||
case 1:
|
||||
t->device_locator = smbios_add_string(t->eos, "DIMM-B");
|
||||
break;
|
||||
default:
|
||||
t->device_locator = smbios_add_string(t->eos, "UNKNOWN");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pad_config gpio_unused[] = {
|
||||
/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
|
||||
/* SUSACK# */ PAD_NC(GPP_A15, NONE),
|
||||
/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
|
||||
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
|
||||
};
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
|
||||
{
|
||||
const struct pad_config *gpio_table;
|
||||
size_t num_gpios;
|
||||
|
||||
gpio_table = variant_gpio_table(&num_gpios);
|
||||
cnl_configure_pads(gpio_table, num_gpios);
|
||||
|
||||
/* Disable unused pads for devices with board ID > 2 */
|
||||
if (board_id() > 2)
|
||||
gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
|
||||
}
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <ec/google/wilco/romstage.h>
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct cnl_mb_cfg memcfg = {
|
||||
/* Access memory info through SMBUS. */
|
||||
.spd[0] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa0},
|
||||
},
|
||||
.spd[1] = {.read_type = NOT_EXISTING},
|
||||
.spd[2] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa4},
|
||||
},
|
||||
.spd[3] = {.read_type = NOT_EXISTING},
|
||||
|
||||
/*
|
||||
* The dqs_map arrays map the ddr4 pins to the SoC pins
|
||||
* for both channels.
|
||||
*
|
||||
* the index = pin number on ddr4 part
|
||||
* the value = pin number on SoC
|
||||
*/
|
||||
.dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7},
|
||||
.dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7},
|
||||
|
||||
/* Baseboard uses 121, 81 and 100 rcomp resistors */
|
||||
.rcomp_resistor = {121, 81, 100},
|
||||
|
||||
/*
|
||||
* Baseboard Rcomp target values.
|
||||
*/
|
||||
.rcomp_targets = {100, 40, 20, 20, 26},
|
||||
|
||||
/* Disable Early Command Training */
|
||||
.ect = 0,
|
||||
|
||||
/* Base on board design */
|
||||
.vref_ca_config = 2,
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
wilco_ec_romstage_init();
|
||||
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <boardid.h>
|
||||
#include <ec/google/wilco/commands.h>
|
||||
#include <smbios.h>
|
||||
#include <variant/variant.h>
|
||||
|
||||
uint32_t sku_id(void)
|
||||
{
|
||||
if (wilco_ec_signed_fw())
|
||||
return VARIANT_SKU_ID_SIGNED_EC;
|
||||
else
|
||||
return VARIANT_SKU_ID;
|
||||
}
|
||||
|
||||
const char *smbios_system_sku(void)
|
||||
{
|
||||
if (wilco_ec_signed_fw())
|
||||
return VARIANT_SKU_NAME_SIGNED_EC;
|
||||
else
|
||||
return VARIANT_SKU_NAME;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/google/wilco/smm.h>
|
||||
#include <soc/smm.h>
|
||||
#include <variant/ec.h>
|
||||
|
||||
void mainboard_smi_espi_handler(void)
|
||||
{
|
||||
wilco_ec_smi_espi();
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
wilco_ec_smi_sleep(slp_typ);
|
||||
}
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
wilco_ec_smi_apmc(apmc);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright 2018 Google LLC
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
bootblock-y += gpio.c
|
||||
ramstage-y += gpio.c
|
||||
romstage-y += gpio.c
|
||||
verstage-y += gpio.c
|
||||
|
|
@ -0,0 +1,393 @@
|
|||
chip soc/intel/cannonlake
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "PMC_GPP_A"
|
||||
register "gpe0_dw1" = "PMC_GPP_C"
|
||||
register "gpe0_dw2" = "PMC_GPP_D"
|
||||
|
||||
# EC host command ranges
|
||||
register "gen1_dec" = "0x00040931" # 0x930-0x937
|
||||
register "gen2_dec" = "0x00040941" # 0x940-0x947
|
||||
register "gen3_dec" = "0x000c0951" # 0x950-0x95f
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "SaGv_Enabled"
|
||||
register "HeciEnabled" = "0"
|
||||
register "SataSalpSupport" = "1"
|
||||
register "SataMode" = "Sata_AHCI"
|
||||
register "SataPortsEnable[2]" = "1"
|
||||
register "SataPortsDevSlp[2]" = "1"
|
||||
register "InternalGfx" = "1"
|
||||
register "SkipExtGfxScan" = "1"
|
||||
register "PchPmSlpS3MinAssert" = "3" # 50ms
|
||||
register "PchPmSlpS4MinAssert" = "4" # 4s
|
||||
register "PchPmSlpSusMinAssert" = "4" # 4s
|
||||
register "PchPmSlpAMinAssert" = "4" # 2s
|
||||
register "PchUnlockGpioPads" = "1"
|
||||
|
||||
register "speed_shift_enable" = "1"
|
||||
register "psys_pmax" = "140"
|
||||
register "s0ix_enable" = "1"
|
||||
register "dptf_enable" = "1"
|
||||
register "dmipwroptimize" = "1"
|
||||
register "satapwroptimize" = "1"
|
||||
register "tdp_pl1_override" = "25"
|
||||
register "tdp_pl2_override" = "51"
|
||||
register "Device4Enable" = "1"
|
||||
register "AcousticNoiseMitigation" = "1"
|
||||
register "SlowSlewRateForIa" = "2"
|
||||
register "SlowSlewRateForGt" = "2"
|
||||
register "SlowSlewRateForSa" = "0"
|
||||
register "SlowSlewRateForFivr" = "2"
|
||||
# Enable eDP device
|
||||
register "DdiPortEdp" = "1"
|
||||
# Enable HPD for DDI ports B/C
|
||||
register "DdiPortBHpd" = "1"
|
||||
register "DdiPortCHpd" = "1"
|
||||
# Enable DDC for DDI port B
|
||||
register "DdiPortBDdc" = "1"
|
||||
|
||||
# VR Settings Configuration for 4 Domains
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
#| Domain/Setting | SA | IA | GTUS | GTS |
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
#| Psi1Threshold | 20A | 20A | 20A | 20A |
|
||||
#| Psi2Threshold | 5A | 5A | 5A | 5A |
|
||||
#| Psi3Threshold | 1A | 1A | 1A | 1A |
|
||||
#| Psi3Enable | 1 | 1 | 1 | 1 |
|
||||
#| Psi4Enable | 1 | 1 | 1 | 1 |
|
||||
#| ImonSlope | 0 | 0 | 0 | 0 |
|
||||
#| ImonOffset | 0 | 0 | 0 | 0 |
|
||||
#| IccMax | 6A | 70A | 31A | 31A |
|
||||
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
|
||||
#| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
|
||||
#| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(6),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 1030,
|
||||
.dc_loadline = 1030,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_IA_CORE]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(70),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 180,
|
||||
.dc_loadline = 180,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(31),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 310,
|
||||
.dc_loadline = 310,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(31),
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 310,
|
||||
.dc_loadline = 310,
|
||||
}"
|
||||
|
||||
# Intel Common SoC Config
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
|
||||
register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port
|
||||
register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port
|
||||
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
|
||||
register "usb2_ports[6]" = "{
|
||||
.enable = 1, \
|
||||
.ocpin = OC_SKIP, \
|
||||
.tx_bias = USB2_BIAS_0MV, \
|
||||
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
|
||||
.pre_emp_bias = USB2_BIAS_28P15MV, \
|
||||
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
|
||||
}" # WWAN
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
|
||||
register "usb3_ports[4]" = "USB3_PORT_EMPTY"
|
||||
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
|
||||
#| I2C0 | Touchscreen |
|
||||
#| I2C1 | Touchpad |
|
||||
#| I2C4 | H1 TPM |
|
||||
#+-------------------+---------------------------+
|
||||
|
||||
register "tcc_offset" = "1"
|
||||
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 52,
|
||||
.fall_time_ns = 110,
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 52,
|
||||
.fall_time_ns = 110,
|
||||
.data_hold_time_ns = 330,
|
||||
},
|
||||
.i2c[4] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 36,
|
||||
.fall_time_ns = 99,
|
||||
},
|
||||
}"
|
||||
|
||||
# PCIe port 10 for M.2 2230 WLAN
|
||||
register "PcieRpEnable[9]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "9"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
|
||||
# PCIe port 11 for card reader
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpLtrEnable[10]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "10"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
|
||||
# PCIe port 13 for M.2 2280 SSD
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieRpLtrEnable[12]" = "1"
|
||||
register "PcieClkSrcUsage[4]" = "12"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
|
||||
# GPIO PM programming
|
||||
register "gpio_override_pm" = "1"
|
||||
|
||||
# GPIO community PM configuration
|
||||
register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
|
||||
register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN |
|
||||
MISCCFG_GPRTCDLCGEN |
|
||||
MISCCFG_GSXSLCGEN |
|
||||
MISCCFG_GPDPCGEN |
|
||||
MISCCFG_GPDLCGEN"
|
||||
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
|
||||
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
|
||||
register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 13.0 on # Integrated Sensor Hub
|
||||
chip drivers/intel/ish
|
||||
register "firmware_name" = ""drallion_ish.bin""
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device pci 14.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Root Hub""
|
||||
register "type" = "UPC_TYPE_HUB"
|
||||
device usb 0.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Type-C Port""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 2.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Type-A Port""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 2.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Right Type-A Port""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device usb 2.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USH""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Fingerprint""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H15)"
|
||||
device usb 2.9 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Type-C Port""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 3.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Type-A Port""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 3.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Right Type-A Port""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device usb 3.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 3.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
chip drivers/intel/wifi
|
||||
register "wake" = "PME_B0_EN_BIT"
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
end
|
||||
device pci 14.5 off end # SDCard
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""WCOM48E2""
|
||||
register "generic.desc" = ""Wacom Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
|
||||
register "generic.reset_delay_ms" = "20"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
|
||||
register "generic.enable_delay_ms" = "55"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "generic.disable_gpio_export_in_crs" = "1"
|
||||
register "hid_desc_reg_offset" = "0x1"
|
||||
device i2c 0A on end
|
||||
end
|
||||
end # I2C #0
|
||||
device pci 15.1 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
|
||||
register "probed" = "1"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 off end # eMMC
|
||||
device pci 1c.0 off end # PCI Express Port 1 (USB)
|
||||
device pci 1c.1 off end # PCI Express Port 2 (USB)
|
||||
device pci 1c.2 off end # PCI Express Port 3 (USB)
|
||||
device pci 1c.3 off end # PCI Express Port 4 (USB)
|
||||
device pci 1c.4 off end # PCI Express Port 5 (USB)
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on
|
||||
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
|
||||
end # PCI Express Port 9
|
||||
device pci 1d.1 on end # PCI Express Port 10
|
||||
device pci 1d.2 on end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 on
|
||||
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
|
||||
end # PCI Express Port 13 (x4)
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on
|
||||
chip ec/google/wilco
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end # LPC/eSPI
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,279 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <variant/gpio.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* RCIN# */ PAD_NC(GPP_A0, NONE),
|
||||
/* ESPI_IO0 */
|
||||
/* ESPI_IO1 */
|
||||
/* ESPI_IO2 */
|
||||
/* ESPI_IO3 */
|
||||
/* ESPI_CS# */
|
||||
/* SERIRQ */
|
||||
/* PIRQA# */ PAD_NC(GPP_A7, NONE),
|
||||
/* CLKRUN# */ PAD_NC(GPP_A8, NONE),
|
||||
/* ESPI_CLK */
|
||||
/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),
|
||||
/* PME# */ PAD_NC(GPP_A11, NONE),
|
||||
/* ISH_LID_CL#_TAB */
|
||||
/* ISH_GP6 */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2),
|
||||
/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
|
||||
/* ESPI_RESET# */
|
||||
/* SUSACK# */ PAD_NC(GPP_A15, NONE),
|
||||
/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
|
||||
/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
|
||||
/* ISH_ACC1_INT# */
|
||||
/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
/* ISH_ACC2_INT# */
|
||||
/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
|
||||
/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
|
||||
/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
|
||||
/* ISH_NB_MODE */
|
||||
/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
|
||||
/* ISH_LID_CL#_NB */
|
||||
/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
|
||||
|
||||
/* CORE_VID0 */
|
||||
/* CORE_VID1 */
|
||||
/* VRALERT# */ PAD_NC(GPP_B2, NONE),
|
||||
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
|
||||
EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
|
||||
/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
|
||||
/* LAN_CLKREQ_CPU_N */
|
||||
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
/* CARD_CLKREQ_CPU_N */
|
||||
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
|
||||
/* WLAN_CLKREQ_CPU_N */
|
||||
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
|
||||
/* WWAN_CLKREQ_CPU_N */
|
||||
/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
|
||||
/* SSD_CKLREQ_CPU_N */
|
||||
/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */
|
||||
/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
|
||||
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */
|
||||
/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */
|
||||
/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */
|
||||
/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
|
||||
/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
|
||||
/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
|
||||
/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
|
||||
/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
|
||||
/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),
|
||||
|
||||
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */
|
||||
/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */
|
||||
/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K),
|
||||
/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */
|
||||
/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */
|
||||
/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K),
|
||||
/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */
|
||||
/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */
|
||||
/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */
|
||||
/* UART0_TXD */ PAD_NC(GPP_C9, NONE),
|
||||
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
|
||||
/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
|
||||
/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
|
||||
EDGE_SINGLE), /* SIO_EXT_WAKE# */
|
||||
/* UART1_TXD */ PAD_NC(GPP_C13, NONE),
|
||||
/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */
|
||||
/* UART1_CTS# */ PAD_NC(GPP_C15, NONE),
|
||||
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */
|
||||
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */
|
||||
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */
|
||||
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */
|
||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
|
||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
|
||||
/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
|
||||
/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
|
||||
LEVEL, NONE), /* TS_INT# */
|
||||
|
||||
/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST,
|
||||
EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
|
||||
/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),
|
||||
/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */
|
||||
/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE),
|
||||
/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */
|
||||
/* ISH_I2C0_ACC_SDA */
|
||||
/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
/* ISH_I2C0_ACC_SCL */
|
||||
/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
|
||||
/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
|
||||
/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */
|
||||
/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE),
|
||||
/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */
|
||||
/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE),
|
||||
/* ISH_CPU_UART0_RX */
|
||||
/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1),
|
||||
/* ISH_CPU_UART0_TX */
|
||||
/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
|
||||
/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
|
||||
/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
|
||||
/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
|
||||
/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
|
||||
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
|
||||
/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),
|
||||
/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),
|
||||
/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */
|
||||
/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */
|
||||
/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP,
|
||||
EDGE_SINGLE), /* WWAN_GPIO_WAKE# */
|
||||
|
||||
/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE),
|
||||
/* M3042_PCIE#_SATA */
|
||||
/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
/* M2880_PCIE_SATA# */
|
||||
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
|
||||
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
|
||||
/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),
|
||||
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */
|
||||
/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */
|
||||
/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */
|
||||
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
|
||||
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */
|
||||
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */
|
||||
/* USB2_OC2# */ PAD_NC(GPP_E11, NONE),
|
||||
/* USB2_OC3# */ PAD_NC(GPP_E12, NONE),
|
||||
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */
|
||||
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */
|
||||
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
|
||||
/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */
|
||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */
|
||||
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */
|
||||
/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
|
||||
/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
|
||||
/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
|
||||
/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */
|
||||
/* GPP_F1 */ PAD_NC(GPP_F1, NONE),
|
||||
/* GPP_F2 */ PAD_NC(GPP_F2, NONE),
|
||||
/* GPP_F3 */ PAD_NC(GPP_F3, NONE),
|
||||
/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
|
||||
/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */
|
||||
/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */
|
||||
/* GPP_F10 */ PAD_NC(GPP_F10, NONE),
|
||||
/* EMMC_CMD */ PAD_NC(GPP_F11, NONE),
|
||||
/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE),
|
||||
/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE),
|
||||
/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE),
|
||||
/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE),
|
||||
/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE),
|
||||
/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE),
|
||||
/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE),
|
||||
/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE),
|
||||
/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE),
|
||||
/* EMMC_CLK */ PAD_NC(GPP_F21, NONE),
|
||||
/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE),
|
||||
/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */
|
||||
/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */
|
||||
/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */
|
||||
/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
|
||||
/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */
|
||||
/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */
|
||||
/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */
|
||||
/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */
|
||||
|
||||
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),
|
||||
/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */
|
||||
/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */
|
||||
/* I2S2_RXD */ PAD_NC(GPP_H3, NONE),
|
||||
/* I2C2_SDA */ PAD_NC(GPP_H4, NONE),
|
||||
/* I2C2_SCL */ PAD_NC(GPP_H5, NONE),
|
||||
/* I2C3_SDA */ PAD_NC(GPP_H6, NONE),
|
||||
/* I2C3_SCL */ PAD_NC(GPP_H7, NONE),
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
|
||||
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
|
||||
/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */
|
||||
/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */
|
||||
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
|
||||
/* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
|
||||
/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),
|
||||
/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE),
|
||||
/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */
|
||||
/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE),
|
||||
/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE),
|
||||
/* GPP_H21 */ PAD_NC(GPP_H21, NONE),
|
||||
/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */
|
||||
/* GPP_H23 */ PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */
|
||||
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */
|
||||
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */
|
||||
/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */
|
||||
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */
|
||||
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */
|
||||
/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */
|
||||
/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */
|
||||
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */
|
||||
/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */
|
||||
/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */
|
||||
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
|
||||
/* SSD RESET pin will stay low first */
|
||||
/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
|
||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
|
||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
|
||||
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
|
||||
/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
|
||||
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
|
||||
/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
|
||||
/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
|
||||
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
|
||||
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
|
||||
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
|
||||
/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define DPTF_CPU_PASSIVE 98
|
||||
#define DPTF_CPU_CRITICAL 108
|
||||
|
||||
/* Skin Sensor for CPU VR temperature monitor */
|
||||
#define DPTF_TSR0_SENSOR_ID 1
|
||||
#define DPTF_TSR0_SENSOR_NAME "Skin"
|
||||
#define DPTF_TSR0_PASSIVE 55
|
||||
#define DPTF_TSR0_CRITICAL 100
|
||||
|
||||
/* Memory Sensor for DDR temperature monitor */
|
||||
#define DPTF_TSR1_SENSOR_ID 2
|
||||
#define DPTF_TSR1_SENSOR_NAME "DDR"
|
||||
#define DPTF_TSR1_PASSIVE 53
|
||||
#define DPTF_TSR1_CRITICAL 100
|
||||
|
||||
/* M.2 Sensor for Ambient temperature monitor */
|
||||
#define DPTF_TSR2_SENSOR_ID 3
|
||||
#define DPTF_TSR2_SENSOR_NAME "Ambient"
|
||||
#define DPTF_TSR2_PASSIVE 38
|
||||
#define DPTF_TSR2_CRITICAL 93
|
||||
|
||||
#undef DPTF_ENABLE_FAN_CONTROL
|
||||
#undef DPTF_ENABLE_CHARGER
|
||||
|
||||
Name (DTRT, Package () {
|
||||
/* CPU Throttle Effect on CPU */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Throttle Effect on Skin (TSR0) */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 },
|
||||
|
||||
/* CPU Throttle Effect on DDR (TSR1) */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 },
|
||||
|
||||
/* CPU Throttle Effect on Ambient (TSR2) */
|
||||
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 },
|
||||
})
|
||||
|
||||
Name (MPPC, Package ()
|
||||
{
|
||||
0x2, /* Revision */
|
||||
Package () { /* Power Limit 1 */
|
||||
0, /* PowerLimitIndex, 0 for Power Limit 1 */
|
||||
3000, /* PowerLimitMinimum */
|
||||
21000, /* PowerLimitMaximum */
|
||||
28000, /* TimeWindowMinimum */
|
||||
28000, /* TimeWindowMaximum */
|
||||
100 /* StepSize */
|
||||
},
|
||||
Package () { /* Power Limit 2 */
|
||||
1, /* PowerLimitIndex, 1 for Power Limit 2 */
|
||||
15000, /* PowerLimitMinimum */
|
||||
51000, /* PowerLimitMaximum */
|
||||
28000, /* TimeWindowMinimum */
|
||||
28000, /* TimeWindowMaximum */
|
||||
100 /* StepSize */
|
||||
}
|
||||
})
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2019 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define CAM_EN GPP_B11 /* Active low */
|
||||
#define TS_PD GPP_E7
|
||||
|
||||
/* Method called from LPIT prior to enter s0ix state */
|
||||
Method (MS0X, 1)
|
||||
{
|
||||
If (Arg0) {
|
||||
/* Turn off camera power */
|
||||
\_SB.PCI0.STXS (CAM_EN)
|
||||
} Else {
|
||||
/* Turn on camera power */
|
||||
\_SB.PCI0.CTXS (CAM_EN)
|
||||
}
|
||||
}
|
||||
|
||||
/* Method called from _PTS prior to enter sleep state */
|
||||
Method (MPTS, 1)
|
||||
{
|
||||
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
|
||||
|
||||
/* Clear touch screen pd pin to avoid leakage */
|
||||
\_SB.PCI0.CTXS (TS_PD)
|
||||
}
|
||||
|
||||
/* Method called from _WAK prior to wakeup */
|
||||
Method (MWAK, 1)
|
||||
{
|
||||
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef VARIANT_EC_H
|
||||
#define VARIANT_EC_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* EC wake pin */
|
||||
#define EC_WAKE_PIN GPE0_DW1_12
|
||||
|
||||
/* eSPI virtual wire reporting */
|
||||
#define EC_SCI_GPI GPE0_ESPI
|
||||
|
||||
/* Enable PS/2 keyboard */
|
||||
#define SIO_EC_ENABLE_PS2K
|
||||
|
||||
/* Enable DPTF */
|
||||
#define EC_ENABLE_DPTF
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Flash Write Protect */
|
||||
#define GPIO_PCH_WP GPP_E15
|
||||
|
||||
/* Recovery mode */
|
||||
#define GPIO_REC_MODE GPP_E8
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
|
||||
struct cros_gpio;
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_HDA_VERB_H
|
||||
#define MAINBOARD_HDA_VERB_H
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0295, // Codec Vendor / Device ID: Realtek ALC3204
|
||||
0xffffffff, // Subsystem ID
|
||||
0x0000002b, // Number of jacks (NID entries)
|
||||
|
||||
/* Rest Codec First */
|
||||
AZALIA_RESET(0x1),
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
|
||||
AZALIA_SUBVENDOR(0x0, 0x102808b6),
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130),
|
||||
AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0x0, 0x16, 0x40000000),
|
||||
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030),
|
||||
AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x1d, 0x40c00001),
|
||||
AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2),
|
||||
AZALIA_PIN_CFG(0x0, 0x21, 0x04211020),
|
||||
|
||||
/* D reset */
|
||||
0x0205003C,
|
||||
0x0204F254,
|
||||
0x0205003C,
|
||||
0x0204F214,
|
||||
/* JD1 - 2port JD mode */
|
||||
0x02050009,
|
||||
0x0204E003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
/* Set TRS type-1 */
|
||||
0x02050045,
|
||||
0x02045289,
|
||||
0x02050049,
|
||||
0x02040049,
|
||||
/* Set TRS type-2 + Set UAJ Line2 vref(ALC3254) */
|
||||
0x0205004A,
|
||||
0x0204A830,
|
||||
0x02050063,
|
||||
0x0204CF00,
|
||||
/* NID 0x20 set class-D to 2W@4ohm (+12dB gain)
|
||||
* + Set sine tone gain(0x34) */
|
||||
0x02050038,
|
||||
0x02043909,
|
||||
0x05C50000,
|
||||
0x05C43482,
|
||||
/* AGC-1 Disable + (Front Gain=0dB ) */
|
||||
0x05D50006,
|
||||
0x05D44C50,
|
||||
0x05D50002,
|
||||
0x05D44004,
|
||||
/* AGC-2 (Backt Boost Gain= -0.375dB ,Limiter = -3dB) */
|
||||
0x05D50003,
|
||||
0x05D45E5E,
|
||||
0x05D50001,
|
||||
0x05D4D788,
|
||||
/* AGC-3 + AGC Enable */
|
||||
0x05D50009,
|
||||
0x05D451FF,
|
||||
0x05D50006,
|
||||
0x05D44E50,
|
||||
/* HP-JD Enable +Nokia type */
|
||||
0x0205004A,
|
||||
0x02042010,
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
/* EAPD set to verb-control + I2C Un-use+ DVDD3.3V */
|
||||
0x02050010,
|
||||
0x02040020,
|
||||
0x02050034,
|
||||
0x0204A23D,
|
||||
/* Class D silent detection Enable -84dB threshold */
|
||||
0x02050030,
|
||||
0x02049000,
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
/* Disable EQ + set 250Hz 3rd High Pass filter */
|
||||
0x05350000,
|
||||
0x0534203A,
|
||||
0x05350000,
|
||||
0x0534203A,
|
||||
/* Left Channel-1 */
|
||||
0x0535001d,
|
||||
0x05340800,
|
||||
0x0535001e,
|
||||
0x05340800,
|
||||
/* Left Channel-2 */
|
||||
0x05350003,
|
||||
0x05341EF8,
|
||||
0x05350004,
|
||||
0x05340000,
|
||||
/* Left Channel-3 */
|
||||
0x05350005,
|
||||
0x053403EE,
|
||||
0x05350006,
|
||||
0x0534FA60,
|
||||
/* Left Channel-4 */
|
||||
0x05350007,
|
||||
0x05341E10,
|
||||
0x05350008,
|
||||
0x05347B86,
|
||||
/* Left Channel-5 */
|
||||
0x05350009,
|
||||
0x053401F7,
|
||||
0x0535000A,
|
||||
0x05349FB6,
|
||||
/* Left Channel-6 */
|
||||
0x0535000B,
|
||||
0x05341C00,
|
||||
0x0535000C,
|
||||
0x05340000,
|
||||
/* Left Channel-7 */
|
||||
0x0535000D,
|
||||
0x05340200,
|
||||
0x0535000E,
|
||||
0x05340000,
|
||||
/* Right Channel-1 */
|
||||
0x05450000,
|
||||
0x05442000,
|
||||
0x0545001d,
|
||||
0x05440800,
|
||||
/* Right Channel-2 */
|
||||
0x0545001e,
|
||||
0x05440800,
|
||||
0x05450003,
|
||||
0x05441EF8,
|
||||
/* Right Channel-3 */
|
||||
0x05450004,
|
||||
0x05440000,
|
||||
0x05450005,
|
||||
0x054403EE,
|
||||
/* Right Channel-4 */
|
||||
0x05450006,
|
||||
0x0544FA60,
|
||||
0x05450007,
|
||||
0x05441E10,
|
||||
/* Right Channel-5 */
|
||||
0x05450008,
|
||||
0x05447B86,
|
||||
0x05450009,
|
||||
0x054401F7,
|
||||
/* Right Channel-6 */
|
||||
0x0545000A,
|
||||
0x05449FB6,
|
||||
0x0545000B,
|
||||
0x05441C00,
|
||||
/* Right Channel-7 */
|
||||
0x0545000C,
|
||||
0x05440000,
|
||||
0x0545000D,
|
||||
0x05440200,
|
||||
/* Right Channel-8 + EQ Update & Enable */
|
||||
0x0545000E,
|
||||
0x05440000,
|
||||
0x05350000,
|
||||
0x0534E03A,
|
||||
/* Enable all Microphone */
|
||||
0x0205000D,
|
||||
0x0204A023,
|
||||
0x0205000D,
|
||||
0x0204A023,
|
||||
/* Enable Internal Speaker (NID14) */
|
||||
0x0205000F,
|
||||
0x02040000,
|
||||
0x0205000F,
|
||||
0x02040000,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
/* PCBeep pass through to NID14 for ePSA test-1 */
|
||||
0x02050036,
|
||||
0x020477D7,
|
||||
0x0143B000,
|
||||
0x01470740,
|
||||
/* PCBeep pass through to NID14 for ePSA test-2 */
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef VARIANT_H
|
||||
#define VARIANT_H
|
||||
|
||||
/* Need to update for Drallion with right SKU IDs*/
|
||||
#define VARIANT_SKU_ID 2
|
||||
#define VARIANT_SKU_NAME "sku2"
|
||||
#define VARIANT_SKU_ID_SIGNED_EC 4
|
||||
#define VARIANT_SKU_NAME_SIGNED_EC "sku4"
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue