Add DCON support.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -36,6 +36,7 @@ entries
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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440 1 e 0 dcon_present
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1008 16 h 0 check_sum
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enumerations
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@ -4,9 +4,69 @@
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <pc80/mc146818rtc.h>
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#include "chip.h"
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#include "../southbridge/amd/cs5536/cs5536_smbus2.h"
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/* Borrowed from mc146818rtc.c */
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#define CMOS_READ(addr) ({ \
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outb((addr),RTC_PORT(0)); \
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inb(RTC_PORT(1)); \
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})
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#define CMOS_WRITE(val, addr) ({ \
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outb((addr),RTC_PORT(0)); \
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outb((val),RTC_PORT(1)); \
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})
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static void write_bit(unsigned char val) {
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unsigned char byte = CMOS_READ(440 / 8);
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/* Don't change it if its already set */
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if ((byte & 1) == (val & 1))
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return;
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byte &= ~1;
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byte |= val & 1;
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CMOS_WRITE(val, 440/8);
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}
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static unsigned short _getsmbusbase(void) {
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unsigned devfn = PCI_DEVFN(0xf, 0);
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device_t dev = dev_find_slot(0x0, devfn);
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unsigned long addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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return (unsigned short) (addr & ~1);
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}
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static void init_dcon(void) {
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int ret = 1;
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unsigned short rev = 0;
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unsigned short iobase = _getsmbusbase();
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printk_debug("CHECKING FOR DCON (%x)\n", iobase);
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/* Get the IO base for the SMBUS */
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rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00);
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if (rev & 0xDC00) {
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printk_debug("DCON FOUND - REV %x\n", rev);
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/* Enable the DCON */
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ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
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if (ret != 0)
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printk_debug("DCON ENABLE FAILED\n", ret);
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}
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else
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printk_debug("DCON NOT FOUND (%x)\n", rev);
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write_bit(rev > 0 ? 1 : 0);
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}
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static void init(struct device *dev) {
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/*
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@ -32,6 +92,8 @@ static void init(struct device *dev) {
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pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
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}
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#endif
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init_dcon();
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printk_debug("OLPC REVA EXIT %s\n", __FUNCTION__);
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}
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