From e3815442925619af88617ab572dff622a42810d1 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Thu, 17 Jul 2014 11:31:57 -0700 Subject: [PATCH] rambi: configure USBPHY_COMPBG by the setting in devicetree.cb USBPHY_COMPBG needs to be configured by project BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly CQ-DEPEND=CL:208557 Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6 Original-Signed-off-by: Kane Chen Original-Reviewed-on: https://chromium-review.googlesource.com/208731 Original-Reviewed-by: Shawn Nematbakhsh (cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4) Signed-off-by: Marc Jones Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75 Reviewed-on: http://review.coreboot.org/8217 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/rambi/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 4f0a016cbe..5914a62608 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/baytrail register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" register "usb2_per_port_lane3" = "0x00049a09" register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" # LPE audio codec settings register "lpe_codec_clk_freq" = "25" # 25MHz clock