x86: mtrr: add hole punching support
Some ranges would use less variable MTRRs if an UC area
can be carved off the top of larger WB range. Implement this
approach by doing 3 passes over each region in the addres space:
1. UC default type. Cover non-UC and non-WB regions with respectie type.
Punch UC hole at upper end of larger WB regions with WB type.
2. UC default type. Cover non-UC regions with respective type.
3. WB default type. Cover non-WB regions with respective type.
The hole at upper end of a region uses the same min alignment of 64MiB.
Below are results using a combination of options. The board this was
tested on has 10 variable MTRRs at its disposal. It has 4GiB of RAM.
IO hole config #1: hole starts at 0xad800000
No CACHE_ROM or WRCOMB resources (takes 4 MTRRs):
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0
0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
MTRR: default type WB/UC MTRR counts: 4/9.
MTRR: WB selected as default type.
MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
No CACHE_ROM. 1 WRCOMB resource (takes 6 MTRRs):
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
MTRR: default type WB/UC MTRR counts: 6/10.
MTRR: WB selected as default type.
MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
CACHE_ROM and no WRCOMB resources (taks 10 MTRRs):
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0
0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
MTRR: default type WB/UC MTRR counts: 11/10.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6
MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6
MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
MTRR: 6 base 0x0000000100000000 mask 0x0000007fc0000000 type 6
MTRR: 7 base 0x0000000140000000 mask 0x0000007ff0000000 type 6
Taking a reserved OS MTRR.
MTRR: 8 base 0x000000014f600000 mask 0x0000007fffe00000 type 0
Taking a reserved OS MTRR.
MTRR: 9 base 0x000000014f800000 mask 0x0000007fff800000 type 0
A combination of CACHE_ROM and WRCOMB just won't work.
IO hole config #2: hole starts at 0x80000000:
No CACHE_ROM or WRCOMB resources (takes 1 MTRR):
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0
0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
MTRR: default type WB/UC MTRR counts: 1/5.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0
No CACHE_ROM. 1 WRCOMB resource (takes 4 MTRRs):
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
MTRR: default type WB/UC MTRR counts: 4/6.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0
MTRR: 1 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
MTRR: 2 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
MTRR: 3 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
CACHE_ROM and no WRCOMB resources (takes 6 MTRRs):
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0
0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
MTRR: default type WB/UC MTRR counts: 9/6.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
MTRR: 2 base 0x0000000100000000 mask 0x0000007f80000000 type 6
MTRR: 3 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0
MTRR: 4 base 0x000000017d000000 mask 0x0000007fff000000 type 0
MTRR: 5 base 0x000000017e000000 mask 0x0000007ffe000000 type 0
CACHE_ROM and 1 WRCOMB resource (takes 7 MTRRs):
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0
0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
MTRR: default type WB/UC MTRR counts: 10/7.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
MTRR: 3 base 0x0000000100000000 mask 0x0000007f80000000 type 6
MTRR: 4 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0
MTRR: 5 base 0x000000017d000000 mask 0x0000007fff000000 type 0
MTRR: 6 base 0x000000017e000000 mask 0x0000007ffe000000 type 0
Change-Id: Iceb9b64991accf558caae2e7b0205951e9bcde44
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2925
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin
Stefan Reinauer
parent
f6f6e13c46
commit
e383442943
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@ -122,6 +122,21 @@ static inline unsigned int fls(unsigned int x)
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#define RANGE_1MB PHYS_TO_RANGE_ADDR(1 << 20)
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#define RANGE_4GB (1 << (ADDR_SHIFT_TO_RANGE_SHIFT(32)))
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/*
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* The default MTRR type selection uses 3 approaches for selecting the
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* optimal number of variable MTRRs. For each range do 3 calculations:
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* 1. UC as default type with no holes at top of range.
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* 2. UC as default using holes at top of range.
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* 3. WB as default.
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* If using holes is optimal for a range when UC is the default type the
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* tag is updated to direct the commit routine to use a hole at the top
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* of a range.
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*/
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#define MTRR_ALGO_SHIFT (8)
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#define MTRR_TAG_MASK ((1 << MTRR_ALGO_SHIFT) - 1)
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/* If the default type is UC use the hole carving algorithm for a range. */
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#define MTRR_RANGE_UC_USE_HOLE (1 << MTRR_ALGO_SHIFT)
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static inline uint32_t range_entry_base_mtrr_addr(struct range_entry *r)
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{
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return PHYS_TO_RANGE_ADDR(range_entry_base(r));
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@ -132,6 +147,11 @@ static inline uint32_t range_entry_end_mtrr_addr(struct range_entry *r)
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return PHYS_TO_RANGE_ADDR(range_entry_end(r));
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}
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static inline int range_entry_mtrr_type(struct range_entry *r)
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{
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return range_entry_tag(r) & MTRR_TAG_MASK;
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}
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static struct memranges *get_physical_address_space(void)
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{
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static struct memranges *addr_space;
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@ -491,9 +511,72 @@ static void calc_var_mtrr_range(struct var_mtrr_state *var_state,
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}
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}
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static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state)
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static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
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struct range_entry *r)
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{
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struct range_entry *r;
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uint32_t a1, a2, b1, b2;
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int mtrr_type;
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struct range_entry *next;
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/*
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* Determine MTRRs based on the following algoirthm for the given entry:
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* +------------------+ b2 = ALIGN_UP(end)
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* | 0 or more bytes | <-- hole is carved out between b1 and b2
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* +------------------+ a2 = b1 = end
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* | |
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* +------------------+ a1 = begin
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*
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* Thus, there are 3 sub-ranges to configure variable MTRRs for.
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*/
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mtrr_type = range_entry_mtrr_type(r);
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a1 = range_entry_base_mtrr_addr(r);
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a2 = range_entry_end_mtrr_addr(r);
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/* The end address is under 1MiB. The fixed MTRRs take
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* precedence over the variable ones. Therefore this range
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* can be ignored. */
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if (a2 < RANGE_1MB)
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return;
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/* Again, the fixed MTRRs take precedence so the beginning
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* of the range can be set to 0 if it starts below 1MiB. */
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if (a1 < RANGE_1MB)
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a1 = 0;
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/* If the range starts above 4GiB the processing is done. */
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if (!var_state->above4gb && a1 >= RANGE_4GB)
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return;
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/* Clip the upper address to 4GiB if addresses above 4GiB
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* are not being processed. */
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if (!var_state->above4gb && a2 > RANGE_4GB)
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a2 = RANGE_4GB;
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b1 = a2;
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b2 = ALIGN_UP(a2, MTRR_MIN_ALIGN);
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/* Check against the next range. If the current range_entry is the
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* last entry then carving a hole is no problem. If the current entry
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* isn't the last entry then check that the last entry covers the
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* entire hole range with the default mtrr type. */
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next = memranges_next_entry(var_state->addr_space, r);
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if (next != NULL &&
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(range_entry_mtrr_type(next) != var_state->def_mtrr_type ||
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range_entry_end_mtrr_addr(next) < b2)) {
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calc_var_mtrr_range(var_state, a1, a2 - a1, mtrr_type);
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return;
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}
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calc_var_mtrr_range(var_state, a1, b2 - a1, mtrr_type);
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calc_var_mtrr_range(var_state, b1, b2 - b1, var_state->def_mtrr_type);
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}
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static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state,
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struct range_entry *r)
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{
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uint32_t a1, a2, b1, b2, c1, c2;
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int mtrr_type;
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/*
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* For each range that meets the non-default type process it in the
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@ -508,13 +591,7 @@ static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state)
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*
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* Thus, there are 3 sub-ranges to configure variable MTRRs for.
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*/
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memranges_each_entry(r, var_state->addr_space) {
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uint32_t a1, a2, b1, b2, c1, c2;
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int mtrr_type = range_entry_tag(r);
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/* Skip default type. */
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if (var_state->def_mtrr_type == mtrr_type)
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continue;
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mtrr_type = range_entry_mtrr_type(r);
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a1 = range_entry_base_mtrr_addr(r);
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c2 = range_entry_end_mtrr_addr(r);
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@ -523,7 +600,7 @@ static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state)
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* precedence over the variable ones. Therefore this range
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* can be ignored. */
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if (c2 < RANGE_1MB)
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continue;
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return;
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/* Again, the fixed MTRRs take precedence so the beginning
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* of the range can be set to 0 if it starts below 1MiB. */
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@ -532,7 +609,7 @@ static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state)
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/* If the range starts above 4GiB the processing is done. */
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if (!var_state->above4gb && a1 >= RANGE_4GB)
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break;
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return;
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/* Clip the upper address to 4GiB if addresses above 4GiB
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* are not being processed. */
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@ -543,7 +620,7 @@ static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state)
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* than the minimum granularity. */
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if ((c2 - a1) < MTRR_MIN_ALIGN) {
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calc_var_mtrr_range(var_state, a1, c2 - a1, mtrr_type);
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continue;
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return;
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}
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b1 = a2 = ALIGN_UP(a1, MTRR_MIN_ALIGN);
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@ -552,7 +629,6 @@ static void setup_var_mtrrs_by_state(struct var_mtrr_state *var_state)
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calc_var_mtrr_range(var_state, a1, a2 - a1, mtrr_type);
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calc_var_mtrr_range(var_state, b1, b2 - b1, mtrr_type);
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calc_var_mtrr_range(var_state, c1, c2 - c1, mtrr_type);
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}
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}
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static int calc_var_mtrrs(struct memranges *addr_space,
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@ -560,6 +636,7 @@ static int calc_var_mtrrs(struct memranges *addr_space,
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{
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int wb_deftype_count;
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int uc_deftype_count;
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struct range_entry *r;
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struct var_mtrr_state var_state;
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/* The default MTRR cacheability type is determined by calculating
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@ -570,15 +647,67 @@ static int calc_var_mtrrs(struct memranges *addr_space,
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var_state.address_bits = address_bits;
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var_state.commit_mtrrs = 0;
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wb_deftype_count = 0;
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uc_deftype_count = 0;
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/*
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* For each range do 3 calculations:
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* 1. UC as default type with no holes at top of range.
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* 2. UC as default using holes at top of range.
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* 3. WB as default.
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* The lowest count is then used as default after totalling all
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* MTRRs. Note that the optimal algoirthm for UC default is marked in
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* the tag of each range regardless of final decision. UC takes
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* precedence in the MTRR archiecture. Therefore, only holes can be
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* used when the type of the region is MTRR_TYPE_WRBACK with
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* MTRR_TYPE_UNCACHEABLE as the default type.
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*/
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memranges_each_entry(r, var_state.addr_space) {
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int mtrr_type;
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mtrr_type = range_entry_mtrr_type(r);
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if (mtrr_type != MTRR_TYPE_UNCACHEABLE) {
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int uc_hole_count;
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int uc_no_hole_count;
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var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE;
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var_state.mtrr_index = 0;
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/* No hole calculation. */
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calc_var_mtrrs_without_hole(&var_state, r);
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uc_no_hole_count = var_state.mtrr_index;
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/* Hole calculation only if type is WB. The 64 number
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* is a count that is unachievable, thus making it
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* a default large number in the case of not doing
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* the hole calculation. */
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uc_hole_count = 64;
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if (mtrr_type == MTRR_TYPE_WRBACK) {
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var_state.mtrr_index = 0;
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calc_var_mtrrs_with_hole(&var_state, r);
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uc_hole_count = var_state.mtrr_index;
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}
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/* Mark the entry with the optimal algorithm. */
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if (uc_no_hole_count < uc_hole_count) {
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uc_deftype_count += uc_no_hole_count;
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} else {
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unsigned long new_tag;
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new_tag = mtrr_type | MTRR_RANGE_UC_USE_HOLE;
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range_entry_update_tag(r, new_tag);
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uc_deftype_count += uc_hole_count;
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}
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}
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if (mtrr_type != MTRR_TYPE_WRBACK) {
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var_state.mtrr_index = 0;
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var_state.def_mtrr_type = MTRR_TYPE_WRBACK;
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setup_var_mtrrs_by_state(&var_state);
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wb_deftype_count = var_state.mtrr_index;
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var_state.mtrr_index = 0;
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var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE;
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setup_var_mtrrs_by_state(&var_state);
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uc_deftype_count = var_state.mtrr_index;
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calc_var_mtrrs_without_hole(&var_state, r);
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wb_deftype_count += var_state.mtrr_index;
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}
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}
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printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n",
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wb_deftype_count, uc_deftype_count);
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@ -594,6 +723,7 @@ static int calc_var_mtrrs(struct memranges *addr_space,
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static void commit_var_mtrrs(struct memranges *addr_space, int def_type,
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int above4gb, int address_bits)
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{
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struct range_entry *r;
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struct var_mtrr_state var_state;
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int i;
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@ -604,7 +734,17 @@ static void commit_var_mtrrs(struct memranges *addr_space, int def_type,
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var_state.commit_mtrrs = 1;
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var_state.mtrr_index = 0;
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var_state.def_mtrr_type = def_type;
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setup_var_mtrrs_by_state(&var_state);
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memranges_each_entry(r, var_state.addr_space) {
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if (range_entry_mtrr_type(r) == def_type)
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continue;
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if (def_type == MTRR_TYPE_UNCACHEABLE &&
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(range_entry_tag(r) & MTRR_RANGE_UC_USE_HOLE))
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calc_var_mtrrs_with_hole(&var_state, r);
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else
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calc_var_mtrrs_without_hole(&var_state, r);
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}
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/* Clear all remaining variable MTTRs. */
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for (i = var_state.mtrr_index; i < total_mtrrs; i++)
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