mb/google/volteer/var/voema: Reduce stop delay time to 150ms for ELAN TS

Set register "generic.stop_delay_ms" to 150 to reduce power resume time.

BUG=b:185308246
TEST=tested on voema

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Idd90191ee7ecbbc544121dc0b93101bea64f0e5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54275
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu 2021-05-13 20:27:19 +08:00 committed by Werner Zeh
parent 2d1f4cb7eb
commit e395cf926a
1 changed files with 1 additions and 1 deletions

View File

@ -71,7 +71,7 @@ chip soc/intel/tigerlake
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)"
register "generic.enable_delay_ms" = "10" register "generic.enable_delay_ms" = "10"
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)"
register "generic.stop_delay_ms" = "300" register "generic.stop_delay_ms" = "150"
register "generic.has_power_resource" = "1" register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1" register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01" register "hid_desc_reg_offset" = "0x01"