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soc/mediatek/mt8186: Enable DCM 

DCM (dynamic clock management) can dynamically slow down or gate clocks
during CPU or bus idle. Enable DCM settings on the MT8186 platform.

TEST=build pass and check register ok
BUG=b:202871018

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Edward-JW Yang 2021-11-01 19:23:52 +08:00 committed by Hung-Te Lin
parent 7c14ff0261
commit e3964c75d7
2 changed files with 46 additions and 0 deletions
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15
src/soc/mediatek/mt8186/include/soc/pll.h
View File

@ -507,4 +507,19 @@ DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0)
DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
DEFINE_BITFIELD(CLK26CALI_0_ENABLE, 12, 12)
DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
DEFINE_BIT(INFRACFG_AO_AUDIO_BUS_REG0, 29)
DEFINE_BIT(INFRACFG_AO_ICUSB_BUS_REG0, 28)
DEFINE_BITFIELD(INFRACFG_AO_INFRA_BUS_REG0_0, 14, 0)
DEFINE_BITFIELD(INFRACFG_AO_INFRA_BUS_REG0_1, 23, 20)
DEFINE_BIT(INFRACFG_AO_INFRA_BUS_REG0_2, 30)
DEFINE_BIT(INFRACFG_AO_P2P_RX_CLK_REG0_MASK_0, 0)
DEFINE_BIT(INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 5)
DEFINE_BITFIELD(INFRACFG_AO_PERI_BUS_REG0_0, 1, 0)
DEFINE_BITFIELD(INFRACFG_AO_PERI_BUS_REG0_1, 27, 3)
DEFINE_BIT(INFRACFG_AO_PERI_BUS_REG0_2, 31)
#endif /* SOC_MEDIATEK_MT8186_PLL_H */

31
src/soc/mediatek/mt8186/pll.c
View File

@ -436,6 +436,37 @@ void mt_pll_init(void)
write32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, 0x805f0603);
write32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, 0xb07f0603);
/* dcm_infracfg_ao_audio_bus and dcm_infracfg_ao_icusb_bus */
SET32_BITFIELDS(&mt8186_infracfg_ao->peri_bus_dcm_ctrl,
INFRACFG_AO_AUDIO_BUS_REG0, 0,
INFRACFG_AO_ICUSB_BUS_REG0, 0,
INFRACFG_AO_AUDIO_BUS_REG0, 1,
INFRACFG_AO_ICUSB_BUS_REG0, 1);
/* dcm_infracfg_ao_infra_bus */
SET32_BITFIELDS(&mt8186_infracfg_ao->infra_bus_dcm_ctrl,
INFRACFG_AO_INFRA_BUS_REG0_0, 0,
INFRACFG_AO_INFRA_BUS_REG0_1, 0,
INFRACFG_AO_INFRA_BUS_REG0_2, 0,
INFRACFG_AO_INFRA_BUS_REG0_0, 0x603,
INFRACFG_AO_INFRA_BUS_REG0_1, 0xF,
INFRACFG_AO_INFRA_BUS_REG0_2, 1);
/* dcm_infracfg_ao_p2p_rx_clk */
SET32_BITFIELDS(&mt8186_infracfg_ao->p2p_rx_clk_on,
INFRACFG_AO_P2P_RX_CLK_REG0_MASK_0, 0,
INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 0,
INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 1);
/* dcm_infracfg_ao_peri_bus */
SET32_BITFIELDS(&mt8186_infracfg_ao->peri_bus_dcm_ctrl,
INFRACFG_AO_PERI_BUS_REG0_0, 0,
INFRACFG_AO_PERI_BUS_REG0_1, 0,
INFRACFG_AO_PERI_BUS_REG0_2, 0,
INFRACFG_AO_PERI_BUS_REG0_0, 3,
INFRACFG_AO_PERI_BUS_REG0_1, 0xFF07C,
INFRACFG_AO_PERI_BUS_REG0_2, 1);
for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);