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intel/cpu: Switch older models to TSC_MONOTONIC_TIMER 

The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.

Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-07-05 18:05:17 +03:00
parent c00e2fb996
commit e39becf521
15 changed files with 15 additions and 160 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/intel/fsp_model_406dx/Kconfig
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@ -26,12 +26,13 @@ config CPU_SPECIFIC_OPTIONS
select SMP
select MMX
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select MICROCODE_BLOB_NOT_IN_BLOB_REPO
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
select TSC_MONOTONIC_TIMER
select TSC_CONSTANT_RATE
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_SMM

4
src/cpu/intel/model_1067x/Kconfig
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@ -6,7 +6,9 @@ config CPU_INTEL_MODEL_1067X
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON

4
src/cpu/intel/model_106cx/Kconfig
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@ -6,7 +6,9 @@ config CPU_INTEL_MODEL_106CX
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SIPI_VECTOR_IN_ROM
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE

4
src/cpu/intel/model_6ex/Kconfig
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@ -6,7 +6,9 @@ config CPU_INTEL_MODEL_6EX
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS

4
src/cpu/intel/model_6fx/Kconfig
View File

@ -6,7 +6,9 @@ config CPU_INTEL_MODEL_6FX
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS

1
src/mainboard/getac/p470/Kconfig
View File

@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_MP_TABLE
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select UDELAY_LAPIC
select BOARD_ROMSIZE_KB_1024
select INTEL_INT15
select I945_LVDS

2
src/northbridge/intel/fsp_rangeley/Makefile.inc
View File

@ -27,8 +27,6 @@ romstage-y += memmap.c
romstage-y += ../../../arch/x86/walkcbfs.S
romstage-y += port_access.c
smm-y += udelay.c
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)
CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/

66
src/northbridge/intel/fsp_rangeley/udelay.c
View File

@ -1,66 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
#define MSR_PLATFORM_INFO 0xce
/**
* Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
*/
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.
* This code is used to prevent use of libgcc's umoddi3.
*/
static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
{
tsc->lo = (a & 0xffff) * (b & 0xffff);
tsc->hi = ((tsc->lo >> 16)
+ ((a & 0xffff) * (b >> 16))
+ ((b & 0xffff) * (a >> 16)));
tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
}
void udelay(u32 us)
{
u32 dword;
tsc_t tsc, tsc1, tscd;
msr_t msr;
u32 fsb = 100, divisor;
u32 d; /* ticks per us */
msr = rdmsr(MSR_PLATFORM_INFO);
divisor = (msr.lo >> 8) & 0xff;
d = fsb * divisor;
multiply_to_tsc(&tscd, us, d);
tsc1 = rdtsc();
dword = tsc1.lo + tscd.lo;
if ((dword < tsc1.lo) || (dword < tscd.lo)) {
tsc1.hi++;
}
tsc1.lo = dword;
tsc1.hi += tscd.hi;
do {
tsc = rdtsc();
} while ((tsc.hi < tsc1.hi)
|| ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
}

1
src/northbridge/intel/gm45/Kconfig
View File

@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_GM45
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select VGA
select INTEL_EDID
select INTEL_GMA_ACPI

2
src/northbridge/intel/gm45/Makefile.inc
View File

@ -35,8 +35,6 @@ ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += gma.c
smm-y += ../../../cpu/x86/lapic/apic_timer.c
postcar-y += memmap.c
endif

1
src/northbridge/intel/i945/Kconfig
View File

@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_I945
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select VGA
select INTEL_GMA_ACPI
select INTEL_GMA_SSC_ALTERNATE_REF

2
src/northbridge/intel/i945/Makefile.inc
View File

@ -27,8 +27,6 @@ romstage-y += errata.c
romstage-y += debug.c
romstage-y += rcven.c
smm-y += udelay.c
postcar-y += memmap.c
endif

77
src/northbridge/intel/i945/udelay.c
View File

@ -1,77 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
/**
* Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
*/
void udelay(u32 us)
{
u32 dword;
tsc_t tsc, tsc1, tscd;
msr_t msr;
u32 fsb = 0, divisor;
u32 d; /* ticks per us */
msr = rdmsr(MSR_FSB_FREQ);
switch (msr.lo & 0x07) {
case 5:
fsb = 400;
break;
case 1:
fsb = 533;
break;
case 3:
fsb = 667;
break;
case 2:
fsb = 800;
break;
case 0:
fsb = 1067;
break;
case 4:
fsb = 1333;
break;
case 6:
fsb = 1600;
break;
}
msr = rdmsr(IA32_PERF_STATUS);
divisor = (msr.hi >> 8) & 0x1f;
d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */
multiply_to_tsc(&tscd, us, d);
tsc1 = rdtsc();
dword = tsc1.lo + tscd.lo;
if ((dword < tsc1.lo) || (dword < tscd.lo))
tsc1.hi++;
tsc1.lo = dword;
tsc1.hi += tscd.hi;
do {
tsc = rdtsc();
} while ((tsc.hi < tsc1.hi)
|| ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
}

1
src/northbridge/intel/pineview/Kconfig
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@ -22,7 +22,6 @@ if NORTHBRIDGE_INTEL_PINEVIEW
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select VGA
select MAINBOARD_HAS_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT

1
src/northbridge/intel/x4x/Kconfig
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@ -22,7 +22,6 @@ if NORTHBRIDGE_INTEL_X4X
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select VGA
select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS