mb/google/taeko: enable DPTF functionality for taeko
Enable DPTF functionality for taeko BRANCH=None BUG=b:203035930 TEST=Built and tested on taeko board Change-Id: Ic9f3cbf5cd52ebc48b274b43fcdb57a51dcf94ec Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Kevin Chang
Felix Held
parent
dd275f7a6c
commit
e3bb49e905
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@ -87,6 +87,123 @@ chip soc/intel/alderlake
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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}"
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device domain 0 on
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device domain 0 on
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DRAM_SOC""
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register "options.tsr[1].desc" = ""Ambient""
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register "options.tsr[2].desc" = ""Charger""
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register "options.tsr[3].desc" = ""WWAN""
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# TODO: below values are initial reference values only
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(85, 90),
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TEMP_PCT(80, 74),
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TEMP_PCT(75, 74),
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TEMP_PCT(70, 74),
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TEMP_PCT(65, 74),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(51, 74),
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TEMP_PCT(47, 60),
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TEMP_PCT(45, 45),
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TEMP_PCT(42, 45),
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TEMP_PCT(37, 35),
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}
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},
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[2] = {
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.target = DPTF_TEMP_SENSOR_2,
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.thresholds = {
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TEMP_PCT(51, 74),
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TEMP_PCT(47, 60),
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TEMP_PCT(45, 45),
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TEMP_PCT(42, 45),
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TEMP_PCT(37, 35),
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}
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},
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[3] = {
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.target = DPTF_TEMP_SENSOR_3,
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.thresholds = {
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TEMP_PCT(51, 74),
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TEMP_PCT(47, 60),
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TEMP_PCT(45, 45),
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TEMP_PCT(42, 45),
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TEMP_PCT(37, 35),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000),
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[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN),
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[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 12000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 55000,
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.max_power = 55000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 100, 6000, 220, 2200, },
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[1] = { 92, 5500, 180, 1800, },
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[2] = { 85, 5000, 145, 1450, },
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[3] = { 74, 4620, 115, 1150, },
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[4] = { 60, 4290, 90, 900, },
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[5] = { 45, 3980, 55, 550, },
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[6] = { 35, 3170, 30, 300, },
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[7] = { 30, 2640, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref tbt_pcie_rp0 off end
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device ref tbt_pcie_rp0 off end
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device ref tbt_pcie_rp1 off end
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device ref tbt_pcie_rp1 off end
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device ref tbt_pcie_rp2 off end
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device ref tbt_pcie_rp2 off end
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