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mb/google/taeko: enable DPTF functionality for taeko 

Enable DPTF functionality for taeko

BRANCH=None
BUG=b:203035930
TEST=Built and tested on taeko board

Change-Id: Ic9f3cbf5cd52ebc48b274b43fcdb57a51dcf94ec
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Kevin Chang 2021-10-15 13:51:49 +08:00 committed by Felix Held
parent dd275f7a6c
commit e3bb49e905
1 changed files with 117 additions and 0 deletions
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117
src/mainboard/google/brya/variants/taeko/overridetree.cb
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@ -87,6 +87,123 @@ chip soc/intel/alderlake
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DRAM_SOC""
register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger""
register "options.tsr[3].desc" = ""WWAN""
# TODO: below values are initial reference values only
## Active Policy
register "policies.active" = "{
[0] = {
.target = DPTF_CPU,
.thresholds = {
TEMP_PCT(85, 90),
TEMP_PCT(80, 74),
TEMP_PCT(75, 74),
TEMP_PCT(70, 74),
TEMP_PCT(65, 74),
}
},
[1] = {
.target = DPTF_TEMP_SENSOR_1,
.thresholds = {
TEMP_PCT(51, 74),
TEMP_PCT(47, 60),
TEMP_PCT(45, 45),
TEMP_PCT(42, 45),
TEMP_PCT(37, 35),
}
},
[2] = {
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
TEMP_PCT(51, 74),
TEMP_PCT(47, 60),
TEMP_PCT(45, 45),
TEMP_PCT(42, 45),
TEMP_PCT(37, 35),
}
},
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
TEMP_PCT(51, 74),
TEMP_PCT(47, 60),
TEMP_PCT(45, 45),
TEMP_PCT(42, 45),
TEMP_PCT(37, 35),
}
}
}"
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000),
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN),
}"
register "controls.power_limits" = "{
.pl1 = {
.min_power = 3000,
.max_power = 12000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 55000,
.max_power = 55000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 1700 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
## Fan Performance Control (Percent, Speed, Noise, Power)
register "controls.fan_perf" = "{
[0] = { 100, 6000, 220, 2200, },
[1] = { 92, 5500, 180, 1800, },
[2] = { 85, 5000, 145, 1450, },
[3] = { 74, 4620, 115, 1150, },
[4] = { 60, 4290, 90, 900, },
[5] = { 45, 3980, 55, 550, },
[6] = { 35, 3170, 30, 300, },
[7] = { 30, 2640, 15, 150, },
[8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, }
}"
## Fan options
register "options.fan.fine_grained_control" = "1"
register "options.fan.step_size" = "2"
device generic 0 alias dptf_policy on end
end
end
device ref tbt_pcie_rp0 off end
device ref tbt_pcie_rp1 off end
device ref tbt_pcie_rp2 off end