soc/intel: Add Lunar Lake device IDs
Added Lunar Lake specific CPU and PCIE device IDs Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Ic0aae6fd7aa8ba3a6a794f8af5ecf3967509b704 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79899 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
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@ -79,5 +79,6 @@
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#define CPUID_RAPTORLAKE_H0 0xb06f5
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#define CPUID_RAPTORLAKE_J0 0xb06a2
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#define CPUID_RAPTORLAKE_Q0 0xb06a3
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#define CPUID_LUNARLAKE_A0_1 0xb06d0
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#endif /* CPU_INTEL_CPU_IDS_H */
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@ -2184,6 +2184,7 @@
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#define PCI_DID_INTEL_MTL_ISHB 0x7e45
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#define PCI_DID_INTEL_ADL_N_ISHB 0x54fc
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#define PCI_DID_INTEL_ADL_P_ISHB 0x51fc
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#define PCI_DID_INTEL_LNL_ISHB 0xa845
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/* Intel 82371FB (PIIX) */
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#define PCI_DID_INTEL_82371FB_ISA 0x122e
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@ -3157,6 +3158,14 @@
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#define PCI_DID_INTEL_RPP_P_ESPI_29 0x519d
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#define PCI_DID_INTEL_RPP_P_ESPI_30 0x519e
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#define PCI_DID_INTEL_RPP_P_ESPI_31 0x519f
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#define PCI_DID_INTEL_LNL_ESPI_0 0xa800
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#define PCI_DID_INTEL_LNL_ESPI_1 0xa801
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#define PCI_DID_INTEL_LNL_ESPI_2 0xa802
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#define PCI_DID_INTEL_LNL_ESPI_3 0xa803
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#define PCI_DID_INTEL_LNL_ESPI_4 0xa804
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#define PCI_DID_INTEL_LNL_ESPI_5 0xa805
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#define PCI_DID_INTEL_LNL_ESPI_6 0xa806
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#define PCI_DID_INTEL_LNL_ESPI_7 0xa807
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/* Intel PCIE device ids */
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#define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10
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@ -3511,6 +3520,15 @@
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#define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d
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#define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d
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#define PCI_DID_INTEL_LNL_PCIE_RP1 0xa838
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#define PCI_DID_INTEL_LNL_PCIE_RP2 0xa839
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#define PCI_DID_INTEL_LNL_PCIE_RP3 0xa83a
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#define PCI_DID_INTEL_LNL_PCIE_RP4 0xa83b
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#define PCI_DID_INTEL_LNL_PCIE_RP5 0xa83c
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#define PCI_DID_INTEL_LNL_PCIE_RP6 0xa83d
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#define PCI_DID_INTEL_LNL_PCIE_RP7 0xa83e
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#define PCI_DID_INTEL_LNL_PCIE_RP8 0xa83f
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#define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38
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#define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39
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#define PCI_DID_INTEL_RPP_S_PCIE_RP3 0x7a3a
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@ -3653,6 +3671,7 @@
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#define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece
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#define PCI_DID_INTEL_RPP_P_PMC 0x51a1
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#define PCI_DID_INTEL_RPP_S_PMC 0x7a21
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#define PCI_DID_INTEL_LNL_PMC 0xa821
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/* Intel I2C device Ids */
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#define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61
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@ -3777,6 +3796,13 @@
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#define PCI_DID_INTEL_MTL_I2C4 0x7e50
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#define PCI_DID_INTEL_MTL_I2C5 0x7e51
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#define PCI_DID_INTEL_LNL_I2C0 0xa878
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#define PCI_DID_INTEL_LNL_I2C1 0xa879
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#define PCI_DID_INTEL_LNL_I2C2 0xa87a
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#define PCI_DID_INTEL_LNL_I2C3 0xa87b
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#define PCI_DID_INTEL_LNL_I2C4 0xa850
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#define PCI_DID_INTEL_LNL_I2C5 0xa851
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/* Intel UART device Ids */
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#define PCI_DID_INTEL_LPT_LP_UART0 0x9c63
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#define PCI_DID_INTEL_LPT_LP_UART1 0x9c64
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@ -3856,6 +3882,10 @@
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#define PCI_DID_INTEL_MTL_UART1 0x7e26
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#define PCI_DID_INTEL_MTL_UART2 0x7e52
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#define PCI_DID_INTEL_LNL_UART0 0xa825
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#define PCI_DID_INTEL_LNL_UART1 0xa826
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#define PCI_DID_INTEL_LNL_UART2 0xa852
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/* Intel SPI device Ids */
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#define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65
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#define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66
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@ -3950,6 +3980,11 @@
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#define PCI_DID_INTEL_MTL_GSPI1 0x7e30
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#define PCI_DID_INTEL_MTL_GSPI2 0x7e46
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#define PCI_DID_INTEL_LNL_HWSEQ_SPI 0xa823
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#define PCI_DID_INTEL_LNL_GSPI0 0xa827
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#define PCI_DID_INTEL_LNL_GSPI1 0xa830
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#define PCI_DID_INTEL_LNL_GSPI2 0xa846
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/* Intel IGD device Ids */
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#define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902
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#define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906
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@ -4111,6 +4146,7 @@
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#define PCI_DID_INTEL_RPL_U_GT3 0xa721
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#define PCI_DID_INTEL_RPL_U_GT4 0xa7ac
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#define PCI_DID_INTEL_RPL_U_GT5 0xa7ad
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#define PCI_DID_INTEL_LNL_M_GT2 0x64a0
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/* Intel Northbridge Ids */
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#define PCI_DID_INTEL_APL_NB 0x5af0
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@ -4248,6 +4284,7 @@
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#define PCI_DID_INTEL_RPL_P_ID_3 0xa708
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#define PCI_DID_INTEL_RPL_P_ID_4 0xa71b
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#define PCI_DID_INTEL_RPL_P_ID_5 0xa71c
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#define PCI_DID_INTEL_LNL_M_ID 0x6400
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/* Intel SMBUS device Ids */
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#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22
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@ -4276,6 +4313,7 @@
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#define PCI_DID_INTEL_MTL_SMBUS 0x7e22
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#define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3
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#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23
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#define PCI_DID_INTEL_LNL_SMBUS 0xa822
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/* Intel EHCI device IDs */
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#define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26
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@ -4316,6 +4354,8 @@
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#define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0
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#define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e
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#define PCI_DID_INTEL_RPP_S_XHCI 0x7a60
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#define PCI_DID_INTEL_LNL_XHCI 0xa87d
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#define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831
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/* Intel P2SB device Ids */
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#define PCI_DID_INTEL_APL_P2SB 0x5a92
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@ -4342,6 +4382,8 @@
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#define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8
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#define PCI_DID_INTEL_RPP_P_P2SB 0x51a0
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#define PCI_DID_INTEL_RPP_S_P2SB 0x7a20
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#define PCI_DID_INTEL_LNL_P2SB 0xa820
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#define PCI_DID_INTEL_LNL_P2SB2 0xa84c
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/* Intel SRAM device Ids */
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#define PCI_DID_INTEL_APL_SRAM 0x5aec
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@ -4356,6 +4398,7 @@
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#define PCI_DID_INTEL_MTL_SOC_SRAM 0x7e7f
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#define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf
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#define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf
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#define PCI_DID_INTEL_LNL_SRAM 0xa87f
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/* Intel AUDIO device Ids */
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#define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20
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@ -4413,6 +4456,15 @@
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#define PCI_DID_INTEL_MTL_AUDIO_7 0x7e2e
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#define PCI_DID_INTEL_MTL_AUDIO_8 0x7e2f
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#define PCI_DID_INTEL_LNL_AUDIO_1 0xa828
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#define PCI_DID_INTEL_LNL_AUDIO_2 0xa829
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#define PCI_DID_INTEL_LNL_AUDIO_3 0xa82a
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#define PCI_DID_INTEL_LNL_AUDIO_4 0xa82b
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#define PCI_DID_INTEL_LNL_AUDIO_5 0xa82c
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#define PCI_DID_INTEL_LNL_AUDIO_6 0xa82d
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#define PCI_DID_INTEL_LNL_AUDIO_7 0xa82e
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#define PCI_DID_INTEL_LNL_AUDIO_8 0xa82f
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/* Intel HECI/ME device Ids */
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#define PCI_DID_INTEL_LPT_H_MEI 0x8c3a
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#define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba
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@ -4457,6 +4509,7 @@
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#define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c
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#define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d
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#define PCI_DID_INTEL_MTL_CSE0 0x7e70
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#define PCI_DID_INTEL_LNL_CSE0 0xa870
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/* Intel XDCI device Ids */
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#define PCI_DID_INTEL_APL_XDCI 0x5aaa
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#define PCI_DID_INTEL_JSP_EMMC 0x4dc4
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#define PCI_DID_INTEL_ADP_EMMC 0x54c4
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/* Intel UFS device Ids */
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#define PCI_DID_INTEL_LNL_UFS 0xa847
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/* Intel Thunderbolt device Ids */
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#define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23
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#define PCI_DID_INTEL_TGL_TBT_RP1 0x9a25
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#define PCI_DID_INTEL_RPL_TBT_RP2 0xa72f
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#define PCI_DID_INTEL_RPL_TBT_DMA0 0xa73e
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#define PCI_DID_INTEL_RPL_TBT_DMA1 0xa76d
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#define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e
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#define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f
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#define PCI_DID_INTEL_LNL_TBT_RP2 0xa860
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#define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833
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#define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834
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/* Intel WIFI Ids */
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#define PCI_DID_1000_SERIES_WIFI 0x0084
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#define PCI_DID_INTEL_ADL_N_IPU 0x462e
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#define PCI_DID_INTEL_MTL_IPU 0x7d19
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#define PCI_DID_INTEL_RPL_IPU 0xa75d
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#define PCI_DID_INTEL_LNL_IPU 0x645d
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/* Intel Dynamic Tuning Technology Device */
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#define PCI_DID_INTEL_CML_DTT 0x1903
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72
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#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3 0x7a73
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#define PCI_DID_INTEL_LNL_CNVI_WIFI_0 0xa840
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#define PCI_DID_INTEL_LNL_CNVI_WIFI_1 0xa841
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#define PCI_DID_INTEL_LNL_CNVI_WIFI_2 0xa842
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#define PCI_DID_INTEL_LNL_CNVI_WIFI_3 0xa843
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#define PCI_DID_INTEL_LNL_CNVI_BT 0xa876
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/* Platform Security Engine */
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#define PCI_DID_INTEL_LNL_PSE0 0xa862
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#define PCI_DID_INTEL_LNL_PSE1 0xa863
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#define PCI_DID_INTEL_LNL_PSE2 0xa864
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/* Intel Crashlog */
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#define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d
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