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soc/intel: Add Lunar Lake device IDs 

Added Lunar Lake specific CPU and PCIE device IDs

Reference:
Lunar Lake External Design Specification Volume 1 (734362)

Change-Id: Ic0aae6fd7aa8ba3a6a794f8af5ecf3967509b704
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79899
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
This commit is contained in:
Appukuttan V K 2024-01-11 17:35:56 +05:30 committed by Felix Held
parent 1b414d14fd
commit e3c507d790
2 changed files with 73 additions and 0 deletions
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1
src/include/cpu/intel/cpu_ids.h
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@ -79,5 +79,6 @@
#define CPUID_RAPTORLAKE_H0 0xb06f5 #define CPUID_RAPTORLAKE_H0 0xb06f5
#define CPUID_RAPTORLAKE_J0 0xb06a2 #define CPUID_RAPTORLAKE_J0 0xb06a2
#define CPUID_RAPTORLAKE_Q0 0xb06a3 #define CPUID_RAPTORLAKE_Q0 0xb06a3
#define CPUID_LUNARLAKE_A0_1 0xb06d0
#endif /* CPU_INTEL_CPU_IDS_H */ #endif /* CPU_INTEL_CPU_IDS_H */

72
src/include/device/pci_ids.h
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@ -2184,6 +2184,7 @@
#define PCI_DID_INTEL_MTL_ISHB 0x7e45 #define PCI_DID_INTEL_MTL_ISHB 0x7e45
#define PCI_DID_INTEL_ADL_N_ISHB 0x54fc #define PCI_DID_INTEL_ADL_N_ISHB 0x54fc
#define PCI_DID_INTEL_ADL_P_ISHB 0x51fc #define PCI_DID_INTEL_ADL_P_ISHB 0x51fc
#define PCI_DID_INTEL_LNL_ISHB 0xa845
/* Intel 82371FB (PIIX) */ /* Intel 82371FB (PIIX) */
#define PCI_DID_INTEL_82371FB_ISA 0x122e #define PCI_DID_INTEL_82371FB_ISA 0x122e
@ -3157,6 +3158,14 @@
#define PCI_DID_INTEL_RPP_P_ESPI_29 0x519d #define PCI_DID_INTEL_RPP_P_ESPI_29 0x519d
#define PCI_DID_INTEL_RPP_P_ESPI_30 0x519e #define PCI_DID_INTEL_RPP_P_ESPI_30 0x519e
#define PCI_DID_INTEL_RPP_P_ESPI_31 0x519f #define PCI_DID_INTEL_RPP_P_ESPI_31 0x519f
#define PCI_DID_INTEL_LNL_ESPI_0 0xa800
#define PCI_DID_INTEL_LNL_ESPI_1 0xa801
#define PCI_DID_INTEL_LNL_ESPI_2 0xa802
#define PCI_DID_INTEL_LNL_ESPI_3 0xa803
#define PCI_DID_INTEL_LNL_ESPI_4 0xa804
#define PCI_DID_INTEL_LNL_ESPI_5 0xa805
#define PCI_DID_INTEL_LNL_ESPI_6 0xa806
#define PCI_DID_INTEL_LNL_ESPI_7 0xa807
/* Intel PCIE device ids */ /* Intel PCIE device ids */
#define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10 #define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10
@ -3511,6 +3520,15 @@
#define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d
#define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d #define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d
#define PCI_DID_INTEL_LNL_PCIE_RP1 0xa838
#define PCI_DID_INTEL_LNL_PCIE_RP2 0xa839
#define PCI_DID_INTEL_LNL_PCIE_RP3 0xa83a
#define PCI_DID_INTEL_LNL_PCIE_RP4 0xa83b
#define PCI_DID_INTEL_LNL_PCIE_RP5 0xa83c
#define PCI_DID_INTEL_LNL_PCIE_RP6 0xa83d
#define PCI_DID_INTEL_LNL_PCIE_RP7 0xa83e
#define PCI_DID_INTEL_LNL_PCIE_RP8 0xa83f
#define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38 #define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38
#define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39 #define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39
#define PCI_DID_INTEL_RPP_S_PCIE_RP3 0x7a3a #define PCI_DID_INTEL_RPP_S_PCIE_RP3 0x7a3a
@ -3653,6 +3671,7 @@
#define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece #define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece
#define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_P_PMC 0x51a1
#define PCI_DID_INTEL_RPP_S_PMC 0x7a21 #define PCI_DID_INTEL_RPP_S_PMC 0x7a21
#define PCI_DID_INTEL_LNL_PMC 0xa821
/* Intel I2C device Ids */ /* Intel I2C device Ids */
#define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61 #define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61
@ -3777,6 +3796,13 @@
#define PCI_DID_INTEL_MTL_I2C4 0x7e50 #define PCI_DID_INTEL_MTL_I2C4 0x7e50
#define PCI_DID_INTEL_MTL_I2C5 0x7e51 #define PCI_DID_INTEL_MTL_I2C5 0x7e51
#define PCI_DID_INTEL_LNL_I2C0 0xa878
#define PCI_DID_INTEL_LNL_I2C1 0xa879
#define PCI_DID_INTEL_LNL_I2C2 0xa87a
#define PCI_DID_INTEL_LNL_I2C3 0xa87b
#define PCI_DID_INTEL_LNL_I2C4 0xa850
#define PCI_DID_INTEL_LNL_I2C5 0xa851
/* Intel UART device Ids */ /* Intel UART device Ids */
#define PCI_DID_INTEL_LPT_LP_UART0 0x9c63 #define PCI_DID_INTEL_LPT_LP_UART0 0x9c63
#define PCI_DID_INTEL_LPT_LP_UART1 0x9c64 #define PCI_DID_INTEL_LPT_LP_UART1 0x9c64
@ -3856,6 +3882,10 @@
#define PCI_DID_INTEL_MTL_UART1 0x7e26 #define PCI_DID_INTEL_MTL_UART1 0x7e26
#define PCI_DID_INTEL_MTL_UART2 0x7e52 #define PCI_DID_INTEL_MTL_UART2 0x7e52
#define PCI_DID_INTEL_LNL_UART0 0xa825
#define PCI_DID_INTEL_LNL_UART1 0xa826
#define PCI_DID_INTEL_LNL_UART2 0xa852
/* Intel SPI device Ids */ /* Intel SPI device Ids */
#define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65 #define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65
#define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66 #define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66
@ -3950,6 +3980,11 @@
#define PCI_DID_INTEL_MTL_GSPI1 0x7e30 #define PCI_DID_INTEL_MTL_GSPI1 0x7e30
#define PCI_DID_INTEL_MTL_GSPI2 0x7e46 #define PCI_DID_INTEL_MTL_GSPI2 0x7e46
#define PCI_DID_INTEL_LNL_HWSEQ_SPI 0xa823
#define PCI_DID_INTEL_LNL_GSPI0 0xa827
#define PCI_DID_INTEL_LNL_GSPI1 0xa830
#define PCI_DID_INTEL_LNL_GSPI2 0xa846
/* Intel IGD device Ids */ /* Intel IGD device Ids */
#define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902
#define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906 #define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906
@ -4111,6 +4146,7 @@
#define PCI_DID_INTEL_RPL_U_GT3 0xa721 #define PCI_DID_INTEL_RPL_U_GT3 0xa721
#define PCI_DID_INTEL_RPL_U_GT4 0xa7ac #define PCI_DID_INTEL_RPL_U_GT4 0xa7ac
#define PCI_DID_INTEL_RPL_U_GT5 0xa7ad #define PCI_DID_INTEL_RPL_U_GT5 0xa7ad
#define PCI_DID_INTEL_LNL_M_GT2 0x64a0
/* Intel Northbridge Ids */ /* Intel Northbridge Ids */
#define PCI_DID_INTEL_APL_NB 0x5af0 #define PCI_DID_INTEL_APL_NB 0x5af0
@ -4248,6 +4284,7 @@
#define PCI_DID_INTEL_RPL_P_ID_3 0xa708 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708
#define PCI_DID_INTEL_RPL_P_ID_4 0xa71b #define PCI_DID_INTEL_RPL_P_ID_4 0xa71b
#define PCI_DID_INTEL_RPL_P_ID_5 0xa71c #define PCI_DID_INTEL_RPL_P_ID_5 0xa71c
#define PCI_DID_INTEL_LNL_M_ID 0x6400
/* Intel SMBUS device Ids */ /* Intel SMBUS device Ids */
#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22
@ -4276,6 +4313,7 @@
#define PCI_DID_INTEL_MTL_SMBUS 0x7e22 #define PCI_DID_INTEL_MTL_SMBUS 0x7e22
#define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3
#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23
#define PCI_DID_INTEL_LNL_SMBUS 0xa822
/* Intel EHCI device IDs */ /* Intel EHCI device IDs */
#define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26
@ -4316,6 +4354,8 @@
#define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0
#define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e #define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e
#define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60
#define PCI_DID_INTEL_LNL_XHCI 0xa87d
#define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831
/* Intel P2SB device Ids */ /* Intel P2SB device Ids */
#define PCI_DID_INTEL_APL_P2SB 0x5a92 #define PCI_DID_INTEL_APL_P2SB 0x5a92
@ -4342,6 +4382,8 @@
#define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8 #define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8
#define PCI_DID_INTEL_RPP_P_P2SB 0x51a0 #define PCI_DID_INTEL_RPP_P_P2SB 0x51a0
#define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20
#define PCI_DID_INTEL_LNL_P2SB 0xa820
#define PCI_DID_INTEL_LNL_P2SB2 0xa84c
/* Intel SRAM device Ids */ /* Intel SRAM device Ids */
#define PCI_DID_INTEL_APL_SRAM 0x5aec #define PCI_DID_INTEL_APL_SRAM 0x5aec
@ -4356,6 +4398,7 @@
#define PCI_DID_INTEL_MTL_SOC_SRAM 0x7e7f #define PCI_DID_INTEL_MTL_SOC_SRAM 0x7e7f
#define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf
#define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf
#define PCI_DID_INTEL_LNL_SRAM 0xa87f
/* Intel AUDIO device Ids */ /* Intel AUDIO device Ids */
#define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20
@ -4413,6 +4456,15 @@
#define PCI_DID_INTEL_MTL_AUDIO_7 0x7e2e #define PCI_DID_INTEL_MTL_AUDIO_7 0x7e2e
#define PCI_DID_INTEL_MTL_AUDIO_8 0x7e2f #define PCI_DID_INTEL_MTL_AUDIO_8 0x7e2f
#define PCI_DID_INTEL_LNL_AUDIO_1 0xa828
#define PCI_DID_INTEL_LNL_AUDIO_2 0xa829
#define PCI_DID_INTEL_LNL_AUDIO_3 0xa82a
#define PCI_DID_INTEL_LNL_AUDIO_4 0xa82b
#define PCI_DID_INTEL_LNL_AUDIO_5 0xa82c
#define PCI_DID_INTEL_LNL_AUDIO_6 0xa82d
#define PCI_DID_INTEL_LNL_AUDIO_7 0xa82e
#define PCI_DID_INTEL_LNL_AUDIO_8 0xa82f
/* Intel HECI/ME device Ids */ /* Intel HECI/ME device Ids */
#define PCI_DID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a
#define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba #define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba
@ -4457,6 +4509,7 @@
#define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c #define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c
#define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d
#define PCI_DID_INTEL_MTL_CSE0 0x7e70 #define PCI_DID_INTEL_MTL_CSE0 0x7e70
#define PCI_DID_INTEL_LNL_CSE0 0xa870
/* Intel XDCI device Ids */ /* Intel XDCI device Ids */
#define PCI_DID_INTEL_APL_XDCI 0x5aaa #define PCI_DID_INTEL_APL_XDCI 0x5aaa
@ -4499,6 +4552,9 @@
#define PCI_DID_INTEL_JSP_EMMC 0x4dc4 #define PCI_DID_INTEL_JSP_EMMC 0x4dc4
#define PCI_DID_INTEL_ADP_EMMC 0x54c4 #define PCI_DID_INTEL_ADP_EMMC 0x54c4
/* Intel UFS device Ids */
#define PCI_DID_INTEL_LNL_UFS 0xa847
/* Intel Thunderbolt device Ids */ /* Intel Thunderbolt device Ids */
#define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23 #define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23
#define PCI_DID_INTEL_TGL_TBT_RP1 0x9a25 #define PCI_DID_INTEL_TGL_TBT_RP1 0x9a25
@ -4532,6 +4588,11 @@
#define PCI_DID_INTEL_RPL_TBT_RP2 0xa72f #define PCI_DID_INTEL_RPL_TBT_RP2 0xa72f
#define PCI_DID_INTEL_RPL_TBT_DMA0 0xa73e #define PCI_DID_INTEL_RPL_TBT_DMA0 0xa73e
#define PCI_DID_INTEL_RPL_TBT_DMA1 0xa76d #define PCI_DID_INTEL_RPL_TBT_DMA1 0xa76d
#define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e
#define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f
#define PCI_DID_INTEL_LNL_TBT_RP2 0xa860
#define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833
#define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834
/* Intel WIFI Ids */ /* Intel WIFI Ids */
#define PCI_DID_1000_SERIES_WIFI 0x0084 #define PCI_DID_1000_SERIES_WIFI 0x0084
@ -4571,6 +4632,7 @@
#define PCI_DID_INTEL_ADL_N_IPU 0x462e #define PCI_DID_INTEL_ADL_N_IPU 0x462e
#define PCI_DID_INTEL_MTL_IPU 0x7d19 #define PCI_DID_INTEL_MTL_IPU 0x7d19
#define PCI_DID_INTEL_RPL_IPU 0xa75d #define PCI_DID_INTEL_RPL_IPU 0xa75d
#define PCI_DID_INTEL_LNL_IPU 0x645d
/* Intel Dynamic Tuning Technology Device */ /* Intel Dynamic Tuning Technology Device */
#define PCI_DID_INTEL_CML_DTT 0x1903 #define PCI_DID_INTEL_CML_DTT 0x1903
@ -4625,6 +4687,16 @@
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3 0x7a73 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3 0x7a73
#define PCI_DID_INTEL_LNL_CNVI_WIFI_0 0xa840
#define PCI_DID_INTEL_LNL_CNVI_WIFI_1 0xa841
#define PCI_DID_INTEL_LNL_CNVI_WIFI_2 0xa842
#define PCI_DID_INTEL_LNL_CNVI_WIFI_3 0xa843
#define PCI_DID_INTEL_LNL_CNVI_BT 0xa876
/* Platform Security Engine */
#define PCI_DID_INTEL_LNL_PSE0 0xa862
#define PCI_DID_INTEL_LNL_PSE1 0xa863
#define PCI_DID_INTEL_LNL_PSE2 0xa864
/* Intel Crashlog */ /* Intel Crashlog */
#define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d