nb/intel/i945: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I181f69372829cf712fd72887b5f2c7134bfcf15a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42190 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Patrick Georgi
parent
c803f65206
commit
e3c68d2e1b
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@ -158,10 +158,7 @@ static void i945_setup_bars(void)
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pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));
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/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
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which requires to have TSEG_BASE aligned to TSEG_SIZE. */
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reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
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reg8 &= ~0x7;
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reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
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pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);
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pci_update_config8(PCI_DEV(0, 0, 0), ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
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@ -505,13 +502,9 @@ static void i945_setup_pci_express_x16(void)
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printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
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reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
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reg16 |= DEVEN_D1F0;
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pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
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pci_or_config16(PCI_DEV(0, 0x00, 0), DEVEN, DEVEN_D1F0);
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reg32 = pci_read_config32(p2peg, PEGCC);
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reg32 &= ~(1 << 8);
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pci_write_config32(p2peg, PEGCC, reg32);
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pci_and_config32(p2peg, PEGCC, ~(1 << 8));
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/* We have no success with querying the usual PCIe registers
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* for link setup success on the i945. Hence we assign a temporary
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@ -531,16 +524,12 @@ static void i945_setup_pci_express_x16(void)
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pci_s_bridge_set_secondary(p2peg, tmp_secondary);
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reg32 = pci_read_config32(p2peg, 0x224);
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reg32 &= ~(1 << 8);
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pci_write_config32(p2peg, 0x224, reg32);
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pci_and_config32(p2peg, 0x224, ~(1 << 8));
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MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0));
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/* Initialize PEG_CAP */
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reg16 = pci_read_config16(p2peg, PEG_CAP);
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reg16 |= (1 << 8);
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pci_write_config16(p2peg, PEG_CAP, reg16);
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pci_or_config16(p2peg, PEG_CAP, 1 << 8);
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/* Setup SLOTCAP */
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/* TODO: These values are mainboard dependent and should be set from devicetree.cb.
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@ -556,8 +545,7 @@ static void i945_setup_pci_express_x16(void)
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/* Wait for training to succeed */
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printk(BIOS_DEBUG, "PCIe link training ...");
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timeout = 0x7ffff;
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while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3)
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&& --timeout)
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while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout)
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;
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reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID);
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@ -569,10 +557,7 @@ static void i945_setup_pci_express_x16(void)
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printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
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reg32 = pci_read_config32(p2peg, PEGSTS);
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reg32 &= ~(0xf << 1);
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reg32 |= 1;
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pci_write_config32(p2peg, PEGSTS, reg32);
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pci_update_config32(p2peg, PEGSTS, ~(0xf << 1), 1);
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/* Force PCIRST# */
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pci_s_assert_secondary_reset(p2peg);
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@ -580,8 +565,7 @@ static void i945_setup_pci_express_x16(void)
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printk(BIOS_DEBUG, "PCIe link training ...");
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timeout = 0x7ffff;
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while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3)
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&& --timeout)
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while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout)
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;
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reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID);
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@ -619,25 +603,17 @@ static void i945_setup_pci_express_x16(void)
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reg16 = (1 << 1);
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pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16);
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reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN);
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reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
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pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32);
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pci_and_config32(PCI_DEV(0, 0x0, 0), DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1));
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}
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/* Enable GPEs */
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reg32 = pci_read_config32(p2peg, PEG_LC);
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reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */
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pci_write_config32(p2peg, PEG_LC, reg32);
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/* Enable GPEs: PMEGPE, HPGPE, GENGPE */
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pci_or_config32(p2peg, PEG_LC, (1 << 2) | (1 << 1) | (1 << 0));
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/* Virtual Channel Configuration: Only VC0 on PCIe x16 */
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reg32 = pci_read_config32(p2peg, VC0RCTL);
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reg32 &= 0xffffff01;
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pci_write_config32(p2peg, VC0RCTL, reg32);
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pci_and_config32(p2peg, VC0RCTL, ~0x000000fe);
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/* Extended VC count */
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reg32 = pci_read_config32(p2peg, PVCCAP1);
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reg32 &= ~(7 << 0);
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pci_write_config32(p2peg, PVCCAP1, reg32);
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pci_and_config32(p2peg, PVCCAP1, ~(7 << 0));
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/* Active State Power Management ASPM */
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@ -653,35 +629,17 @@ static void i945_setup_pci_express_x16(void)
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pci_write_config32(p2peg, 0x228, 0xffffffff);
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/* Program R/WO registers */
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reg32 = pci_read_config32(p2peg, 0x308);
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pci_write_config32(p2peg, 0x308, reg32);
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reg32 = pci_read_config32(p2peg, 0x314);
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pci_write_config32(p2peg, 0x314, reg32);
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reg32 = pci_read_config32(p2peg, 0x324);
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pci_write_config32(p2peg, 0x324, reg32);
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reg32 = pci_read_config32(p2peg, 0x328);
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pci_write_config32(p2peg, 0x328, reg32);
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pci_update_config32(p2peg, 0x308, ~0, 0);
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pci_update_config32(p2peg, 0x314, ~0, 0);
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pci_update_config32(p2peg, 0x324, ~0, 0);
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pci_update_config32(p2peg, 0x328, ~0, 0);
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/* Additional PCIe graphics setup */
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reg32 = pci_read_config32(p2peg, 0xf0);
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reg32 |= (3 << 26);
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pci_write_config32(p2peg, 0xf0, reg32);
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pci_or_config32(p2peg, 0xf0, 3 << 26);
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pci_or_config32(p2peg, 0xf0, 3 << 24);
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pci_or_config32(p2peg, 0xf0, 1 << 5);
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reg32 = pci_read_config32(p2peg, 0xf0);
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reg32 |= (3 << 24);
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pci_write_config32(p2peg, 0xf0, reg32);
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reg32 = pci_read_config32(p2peg, 0xf0);
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reg32 |= (1 << 5);
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pci_write_config32(p2peg, 0xf0, reg32);
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reg32 = pci_read_config32(p2peg, 0x200);
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reg32 &= ~(3 << 26);
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reg32 |= (2 << 26);
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pci_write_config32(p2peg, 0x200, reg32);
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pci_update_config32(p2peg, 0x200, ~(3 << 26), 2 << 26);
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reg32 = pci_read_config32(p2peg, 0xe80);
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if (i945_silicon_revision() >= 2)
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@ -690,13 +648,9 @@ static void i945_setup_pci_express_x16(void)
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reg32 &= ~(1 << 12);
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pci_write_config32(p2peg, 0xe80, reg32);
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reg32 = pci_read_config32(p2peg, 0xeb4);
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reg32 &= ~(1 << 31);
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pci_write_config32(p2peg, 0xeb4, reg32);
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pci_and_config32(p2peg, 0xeb4, ~(1 << 31));
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reg32 = pci_read_config32(p2peg, 0xfc);
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reg32 |= (1 << 31);
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pci_write_config32(p2peg, 0xfc, reg32);
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pci_or_config32(p2peg, 0xfc, 1 << 31);
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if (i945_silicon_revision() >= 3) {
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static const u32 reglist[] = {
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@ -705,12 +659,8 @@ static void i945_setup_pci_express_x16(void)
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(reglist); i++) {
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reg32 = pci_read_config32(p2peg, reglist[i]);
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reg32 &= 0x0fffffff;
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reg32 |= (2 << 28);
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pci_write_config32(p2peg, reglist[i], reg32);
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}
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for (i = 0; i < ARRAY_SIZE(reglist); i++)
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pci_update_config32(p2peg, reglist[i], ~(0xf << 28), 2 << 28);
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}
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if (i945_silicon_revision() <= 2) {
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@ -734,9 +684,7 @@ disable_pciexpress_x16_link:
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/* Toggle PCIRST# */
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pci_s_assert_secondary_reset(p2peg);
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reg32 = pci_read_config32(p2peg, 0x224);
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reg32 |= (1 << 8);
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pci_write_config32(p2peg, 0x224, reg32);
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pci_or_config32(p2peg, 0x224, 1 << 8);
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pci_s_deassert_secondary_reset(p2peg);
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@ -751,9 +699,7 @@ disable_pciexpress_x16_link:
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printk(BIOS_DEBUG, "ok\n");
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/* Finally: Disable the PCI config header */
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reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
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reg16 &= ~DEVEN_D1F0;
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pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
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pci_and_config16(PCI_DEV(0, 0x00, 0), DEVEN, ~DEVEN_D1F0);
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}
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static void i945_setup_root_complex_topology(void)
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@ -795,9 +741,7 @@ static void i945_setup_root_complex_topology(void)
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/* PCI Express x16 Port Root Topology */
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if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) {
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pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR);
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reg32 = pci_read_config32(p2peg, LE1D);
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reg32 |= (1 << 0);
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pci_write_config32(p2peg, LE1D, reg32);
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pci_or_config32(p2peg, LE1D, 1 << 0);
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}
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}
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@ -701,9 +701,7 @@ static void gma_func0_disable(struct device *dev)
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pci_write_config16(dev, GCFC, 0xa00);
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pci_write_config16(dev_host, GGC, (1 << 1));
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unsigned int reg32 = pci_read_config32(dev_host, DEVEN);
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reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
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pci_write_config32(dev_host, DEVEN, reg32);
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pci_and_config32(dev_host, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1));
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dev->enabled = 0;
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}
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@ -730,13 +728,8 @@ static void gma_generate_ssdt(const struct device *device)
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static void gma_func0_read_resources(struct device *dev)
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{
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u8 reg8;
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/* Set Untrusted Aperture Size to 256mb */
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reg8 = pci_read_config8(dev, MSAC);
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reg8 &= ~0x3;
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reg8 |= 0x2;
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pci_write_config8(dev, MSAC, reg8);
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/* Set Untrusted Aperture Size to 256MB */
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pci_update_config8(dev, MSAC, ~0x3, 0x2);
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pci_dev_read_resources(dev);
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}
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@ -257,9 +257,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
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}
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/* Set DRAM initialization bit in ICH7 */
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
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reg8 |= (1<<7);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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pci_or_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, 1 << 7);
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/* clear self refresh status if check is disabled or not a resume */
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if (!CONFIG(CHECK_SLFRCS_ON_RESUME) || sysinfo->boot_path != BOOT_PATH_RESUME) {
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@ -1615,7 +1613,6 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo)
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static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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{
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u8 reg8;
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u16 reg16;
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u8 freq, second_vco, voltage;
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#define CRCLK_166MHz 0x00
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@ -1716,14 +1713,11 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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sysinfo->clkcfg_bit7 = 0;
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/* Graphics Core Render Clock */
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reg16 = pci_read_config16(PCI_DEV(0, 2, 0), GCFC);
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reg16 &= ~((7 << 0) | (1 << 13));
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reg16 |= freq;
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pci_write_config16(PCI_DEV(0, 2, 0), GCFC, reg16);
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pci_update_config16(PCI_DEV(0, 2, 0), GCFC, ~((7 << 0) | (1 << 13)), freq);
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/* Graphics Core Display Clock */
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reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC);
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reg8 &= ~((1<<7) | (7<<4));
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reg8 &= ~((1 << 7) | (7 << 4));
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if (voltage == VOLTAGE_1_05) {
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reg8 |= CDCLK_200MHz;
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@ -1736,7 +1730,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1);
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reg8 |= (1<<3) | (1<<1);
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reg8 |= (1 << 3) | (1 << 1);
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pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
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reg8 |= 0x0f;
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@ -1750,7 +1744,6 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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static void sdram_program_memory_frequency(struct sys_info *sysinfo)
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{
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u32 clkcfg;
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u8 reg8;
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u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
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printk(BIOS_DEBUG, "Setting Memory Frequency... ");
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@ -1795,9 +1788,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
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/* Make sure the following code is in the cache before we execute it. */
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goto cache_code;
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vco_update:
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
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reg8 &= ~(1 << 7);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, (u8)~(1 << 7));
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clkcfg &= ~(1 << 10);
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MCHBAR32(CLKCFG) = clkcfg;
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@ -2142,7 +2133,6 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
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static void sdram_power_management(struct sys_info *sysinfo)
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{
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u8 reg8;
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u16 reg16;
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u32 reg32;
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int integrated_graphics = 1;
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@ -2293,13 +2283,9 @@ static void sdram_power_management(struct sys_info *sysinfo)
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MCHBAR32(FSBPMC4) |= (1 << 4);
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}
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reg8 = pci_read_config8(PCI_DEV(0, 0x0, 0), 0xfc);
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reg8 |= (1 << 4);
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pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
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pci_or_config8(PCI_DEV(0, 0x0, 0), 0xfc, 1 << 4);
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reg8 = pci_read_config8(PCI_DEV(0, 0x2, 0), 0xc1);
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reg8 |= (1 << 2);
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pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
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pci_or_config8(PCI_DEV(0, 0x2, 0), 0xc1, 1 << 2);
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#ifdef C2_SELF_REFRESH_DISABLE
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@ -2729,7 +2715,6 @@ static void sdram_setup_processor_side(void)
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void sdram_initialize(int boot_path, const u8 *spd_addresses)
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{
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struct sys_info sysinfo;
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u8 reg8;
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "Setting up RAM controller.\n");
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@ -2826,9 +2811,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
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sdram_enable_rcomp();
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/* Tell ICH7 that we're done */
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
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reg8 &= ~(1 << 7);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
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pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, (u8)~(1 << 7));
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printk(BIOS_DEBUG, "RAM initialization finished.\n");
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||||
|
||||
|
|
|
|||
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Reference in New Issue