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soc/qualcomm: clock: Clean up clock driver 

Updated return type as CB_SUCCESS and aligned indentation.

BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Taniya Das 2021-06-23 09:08:57 +05:30 committed by Shelley Chen
parent 75a29bc92c
commit e3cf008d88
2 changed files with 4 additions and 5 deletions
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6
src/soc/qualcomm/sc7180/clock.c
View File

@ -164,12 +164,12 @@ static enum cb_err pll_init_and_set(struct sc7180_apss_clock *apss, u32 l_val)
pll_cfg.l_val = l_val;
ret = clock_configure_enable_gpll(&pll_cfg, false, 0);
if (ret < 0)
if (ret != CB_SUCCESS)
return CB_ERR;
pll_cfg.reg_mode = &apss->pll.mode;
ret = agera_pll_enable(&pll_cfg);
if (ret < 0)
if (ret != CB_SUCCESS)
return CB_ERR;
gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK;
@ -224,7 +224,7 @@ int mdss_clock_enable(enum mdss_clock clk_type)
if (clk_type >= MDSS_CLK_COUNT)
return CB_ERR;
/* Enable clock*/
/* Enable clock */
return clock_enable(mdss_cbcr[clk_type]);
}

3
src/soc/qualcomm/sc7280/clock.c
View File

@ -255,7 +255,6 @@ void clock_configure_qspi(uint32_t hz)
clock_enable(&gcc->qspi_core_cbcr);
}
void clock_enable_qup(int qup)
{
struct qupv3_clock *qup_clk;
@ -412,7 +411,7 @@ enum cb_err mdss_clock_enable(enum clk_mdss clk_type)
if (clk_type >= MDSS_CLK_COUNT)
return CB_ERR;
/* Enable clock*/
/* Enable clock */
return clock_enable(mdss_cbcr[clk_type]);
}