google/reks: override USB2 Phy settings on BSW D-Stepping SOC
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings... Base on Intel recommendation, override following settings for USB2 port 1/2/3 on BSW D-stepping SOC. 1. Set USB[1] register for right side to 7321 2. Set USB[2] register for left side to 7021 3. Set USB[3] register for CCD to 7021 Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -18,6 +18,7 @@ romstage-y += romstage.c
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romstage-y += spd_util.c
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romstage-y += spd_util.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += ramstage.c
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SPD_BIN = $(obj)/spd.bin
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SPD_BIN = $(obj)/spd.bin
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@ -0,0 +1,40 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/ramstage.h>
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void board_silicon_USB2_override(SILICON_INIT_UPD *params)
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{
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if (SocStepping() >= SocD0) {
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//D-Stepping
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//USB2[1] right external port
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params->Usb2Port1PerPortPeTxiSet = 7;
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params->Usb2Port1PerPortTxiSet = 3;
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params->Usb2Port1IUsbTxEmphasisEn = 2;
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params->Usb2Port1PerPortTxPeHalf = 1;
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//USB2[2] left external port
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params->Usb2Port2PerPortPeTxiSet = 7;
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params->Usb2Port2PerPortTxiSet = 0;
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params->Usb2Port2IUsbTxEmphasisEn = 2;
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params->Usb2Port2PerPortTxPeHalf = 1;
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//USB2[3] CCD
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params->Usb2Port3PerPortPeTxiSet = 7;
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params->Usb2Port3PerPortTxiSet = 0;
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params->Usb2Port3IUsbTxEmphasisEn = 2;
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params->Usb2Port3PerPortTxPeHalf = 1;
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}
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}
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