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google/reks: override USB2 Phy settings on BSW D-Stepping SOC 

Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings...

Base on Intel recommendation, override following
settings for USB2 port 1/2/3 on BSW D-stepping SOC.

1. Set USB[1] register for right side to 7321
2. Set USB[2] register for left side to 7021
3. Set USB[3] register for CCD to 7021

Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>

Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier 2017-11-01 00:29:34 -05:00 committed by Martin Roth
parent 158170b0a8
commit e3d8471a78
2 changed files with 41 additions and 0 deletions
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1
src/mainboard/google/cyan/variants/reks/Makefile.inc
View File

@ -18,6 +18,7 @@ romstage-y += romstage.c
romstage-y += spd_util.c
ramstage-y += gpio.c
ramstage-y += ramstage.c
SPD_BIN = $(obj)/spd.bin

40
src/mainboard/google/cyan/variants/reks/ramstage.c Normal file
View File

@ -0,0 +1,40 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/ramstage.h>
void board_silicon_USB2_override(SILICON_INIT_UPD *params)
{
if (SocStepping() >= SocD0) {
//D-Stepping
//USB2[1] right external port
params->Usb2Port1PerPortPeTxiSet = 7;
params->Usb2Port1PerPortTxiSet = 3;
params->Usb2Port1IUsbTxEmphasisEn = 2;
params->Usb2Port1PerPortTxPeHalf = 1;
//USB2[2] left external port
params->Usb2Port2PerPortPeTxiSet = 7;
params->Usb2Port2PerPortTxiSet = 0;
params->Usb2Port2IUsbTxEmphasisEn = 2;
params->Usb2Port2PerPortTxPeHalf = 1;
//USB2[3] CCD
params->Usb2Port3PerPortPeTxiSet = 7;
params->Usb2Port3PerPortTxiSet = 0;
params->Usb2Port3IUsbTxEmphasisEn = 2;
params->Usb2Port3PerPortTxPeHalf = 1;
}
}