vc/intel/raptorlake: Add the FSP v4301.01 headers
Move the existing FSP 4221.00 headers for Raptor Lake to a subdirectory called 4221.00_google, and select this if the vendor is Google. Add the standard FSP 4301.01 headers to a separate directory, from Intel download #686654, and select this for all other vendors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
04c49a5e7c
commit
e3d9b0aa3f
|
@ -402,7 +402,9 @@ config FSP_TYPE_IOT
|
||||||
|
|
||||||
config FSP_HEADER_PATH
|
config FSP_HEADER_PATH
|
||||||
string "Location of FSP headers"
|
string "Location of FSP headers"
|
||||||
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO
|
default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_USE_REPO
|
||||||
|
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/4221.00_google/" if VENDOR_GOOGLE && SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO
|
||||||
|
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/4301.01/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO
|
||||||
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT
|
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT
|
||||||
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
|
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
|
||||||
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
|
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
|
||||||
|
|
|
@ -0,0 +1,68 @@
|
||||||
|
/** @file
|
||||||
|
Header file for Firmware Version Information
|
||||||
|
|
||||||
|
@copyright
|
||||||
|
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
|
This program and the accompanying materials are licensed and made available under
|
||||||
|
the terms and conditions of the BSD License which accompanies this distribution.
|
||||||
|
The full text of the license may be found at
|
||||||
|
http://opensource.org/licenses/bsd-license.php
|
||||||
|
|
||||||
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
|
||||||
|
#define _FIRMWARE_VERSION_INFO_HOB_H_
|
||||||
|
|
||||||
|
#include <Uefi/UefiMultiPhase.h>
|
||||||
|
#include <Pi/PiBootMode.h>
|
||||||
|
#include <Pi/PiHob.h>
|
||||||
|
|
||||||
|
#pragma pack(1)
|
||||||
|
///
|
||||||
|
/// Firmware Version Structure
|
||||||
|
///
|
||||||
|
typedef struct {
|
||||||
|
UINT8 MajorVersion;
|
||||||
|
UINT8 MinorVersion;
|
||||||
|
UINT8 Revision;
|
||||||
|
UINT16 BuildNumber;
|
||||||
|
} FIRMWARE_VERSION;
|
||||||
|
|
||||||
|
///
|
||||||
|
/// Firmware Version Information Structure
|
||||||
|
///
|
||||||
|
typedef struct {
|
||||||
|
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
|
||||||
|
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
|
||||||
|
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
|
||||||
|
} FIRMWARE_VERSION_INFO;
|
||||||
|
|
||||||
|
#ifndef __SMBIOS_STANDARD_H__
|
||||||
|
///
|
||||||
|
/// The Smbios structure header.
|
||||||
|
///
|
||||||
|
typedef struct {
|
||||||
|
UINT8 Type;
|
||||||
|
UINT8 Length;
|
||||||
|
UINT16 Handle;
|
||||||
|
} SMBIOS_STRUCTURE;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
///
|
||||||
|
/// Firmware Version Information HOB Structure
|
||||||
|
///
|
||||||
|
typedef struct {
|
||||||
|
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
|
||||||
|
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
|
||||||
|
UINT8 Count; ///< Offset 28 Number of FVI elements included.
|
||||||
|
///
|
||||||
|
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
|
||||||
|
///
|
||||||
|
} FIRMWARE_VERSION_INFO_HOB;
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
#endif // _FIRMWARE_VERSION_INFO_HOB_H_
|
|
@ -0,0 +1,48 @@
|
||||||
|
/** @file
|
||||||
|
|
||||||
|
Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
other materials provided with the distribution.
|
||||||
|
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||||
|
be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||||
|
THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
This file is automatically generated. Please do NOT modify !!!
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
#ifndef __FSPUPD_H__
|
||||||
|
#define __FSPUPD_H__
|
||||||
|
|
||||||
|
#include <FspEas.h>
|
||||||
|
|
||||||
|
#pragma pack(1)
|
||||||
|
|
||||||
|
#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'ADLUPD_T' */
|
||||||
|
|
||||||
|
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'ADLUPD_M' */
|
||||||
|
|
||||||
|
#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'ADLUPD_S' */
|
||||||
|
|
||||||
|
#pragma pack()
|
||||||
|
|
||||||
|
#endif
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,318 @@
|
||||||
|
/** @file
|
||||||
|
This file contains definitions required for creation of
|
||||||
|
Memory S3 Save data, Memory Info data and Memory Platform
|
||||||
|
data hobs.
|
||||||
|
|
||||||
|
@copyright
|
||||||
|
Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.<BR>
|
||||||
|
This program and the accompanying materials are licensed and made available under
|
||||||
|
the terms and conditions of the BSD License that accompanies this distribution.
|
||||||
|
The full text of the license may be found at
|
||||||
|
http://opensource.org/licenses/bsd-license.php.
|
||||||
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
|
|
||||||
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
|
||||||
|
@par Specification Reference:
|
||||||
|
**/
|
||||||
|
#ifndef _MEM_INFO_HOB_H_
|
||||||
|
#define _MEM_INFO_HOB_H_
|
||||||
|
|
||||||
|
|
||||||
|
#pragma pack (push, 1)
|
||||||
|
|
||||||
|
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||||
|
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||||
|
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||||
|
|
||||||
|
#define MAX_NODE 2
|
||||||
|
#define MAX_CH 4
|
||||||
|
#define MAX_DIMM 2
|
||||||
|
#define HOB_MAX_SAGV_POINTS 4
|
||||||
|
|
||||||
|
///
|
||||||
|
/// Host reset states from MRC.
|
||||||
|
///
|
||||||
|
#define WARM_BOOT 2
|
||||||
|
|
||||||
|
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||||
|
#define B_RANK0_PRS BIT0
|
||||||
|
#define B_RANK1_PRS BIT1
|
||||||
|
#define B_RANK2_PRS BIT4
|
||||||
|
#define B_RANK3_PRS BIT5
|
||||||
|
|
||||||
|
// @todo remove and use the MdePkg\Include\Pi\PiHob.h
|
||||||
|
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
|
||||||
|
#ifndef __HOB__H__
|
||||||
|
typedef struct _EFI_HOB_GENERIC_HEADER {
|
||||||
|
UINT16 HobType;
|
||||||
|
UINT16 HobLength;
|
||||||
|
UINT32 Reserved;
|
||||||
|
} EFI_HOB_GENERIC_HEADER;
|
||||||
|
|
||||||
|
typedef struct _EFI_HOB_GUID_TYPE {
|
||||||
|
EFI_HOB_GENERIC_HEADER Header;
|
||||||
|
EFI_GUID Name;
|
||||||
|
///
|
||||||
|
/// Guid specific data goes here
|
||||||
|
///
|
||||||
|
} EFI_HOB_GUID_TYPE;
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
///
|
||||||
|
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||||
|
///
|
||||||
|
|
||||||
|
//
|
||||||
|
// Matches MAX_SPD_SAVE define in MRC
|
||||||
|
//
|
||||||
|
#ifndef MAX_SPD_SAVE
|
||||||
|
#define MAX_SPD_SAVE 29
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//
|
||||||
|
// MRC version description.
|
||||||
|
//
|
||||||
|
typedef struct {
|
||||||
|
UINT8 Major; ///< Major version number
|
||||||
|
UINT8 Minor; ///< Minor version number
|
||||||
|
UINT8 Rev; ///< Revision number
|
||||||
|
UINT8 Build; ///< Build number
|
||||||
|
} SiMrcVersion;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Matches MrcChannelSts enum in MRC
|
||||||
|
//
|
||||||
|
#ifndef CHANNEL_NOT_PRESENT
|
||||||
|
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
|
||||||
|
#endif
|
||||||
|
#ifndef CHANNEL_DISABLED
|
||||||
|
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
|
||||||
|
#endif
|
||||||
|
#ifndef CHANNEL_PRESENT
|
||||||
|
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//
|
||||||
|
// Matches MrcDimmSts enum in MRC
|
||||||
|
//
|
||||||
|
#ifndef DIMM_ENABLED
|
||||||
|
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||||
|
#endif
|
||||||
|
#ifndef DIMM_DISABLED
|
||||||
|
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||||
|
#endif
|
||||||
|
#ifndef DIMM_PRESENT
|
||||||
|
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||||
|
#endif
|
||||||
|
#ifndef DIMM_NOT_PRESENT
|
||||||
|
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//
|
||||||
|
// Matches MrcBootMode enum in MRC
|
||||||
|
//
|
||||||
|
#ifndef __MRC_BOOT_MODE__
|
||||||
|
#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
|
||||||
|
#ifndef INT32_MAX
|
||||||
|
#define INT32_MAX (0x7FFFFFFF)
|
||||||
|
#endif //INT32_MAX
|
||||||
|
typedef enum {
|
||||||
|
bmCold, ///< Cold boot
|
||||||
|
bmWarm, ///< Warm boot
|
||||||
|
bmS3, ///< S3 resume
|
||||||
|
bmFast, ///< Fast boot
|
||||||
|
MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
|
||||||
|
MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
|
||||||
|
} MRC_BOOT_MODE;
|
||||||
|
#endif //__MRC_BOOT_MODE__
|
||||||
|
|
||||||
|
//
|
||||||
|
// Matches MrcDdrType enum in MRC
|
||||||
|
//
|
||||||
|
#ifndef MRC_DDR_TYPE_DDR5
|
||||||
|
#define MRC_DDR_TYPE_DDR5 1
|
||||||
|
#endif
|
||||||
|
#ifndef MRC_DDR_TYPE_LPDDR5
|
||||||
|
#define MRC_DDR_TYPE_LPDDR5 2
|
||||||
|
#endif
|
||||||
|
#ifndef MRC_DDR_TYPE_LPDDR4
|
||||||
|
#define MRC_DDR_TYPE_LPDDR4 3
|
||||||
|
#endif
|
||||||
|
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||||
|
#define MRC_DDR_TYPE_UNKNOWN 4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define MAX_PROFILE_NUM 7 // number of memory profiles supported
|
||||||
|
#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
|
||||||
|
|
||||||
|
#define MAX_TRACE_REGION 5
|
||||||
|
#define MAX_TRACE_CACHE_TYPE 2
|
||||||
|
|
||||||
|
//
|
||||||
|
// DIMM timings
|
||||||
|
//
|
||||||
|
typedef struct {
|
||||||
|
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||||
|
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||||
|
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||||
|
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||||
|
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||||
|
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||||
|
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||||
|
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||||
|
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||||
|
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||||
|
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||||
|
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||||
|
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||||
|
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||||
|
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||||
|
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||||
|
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||||
|
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||||
|
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||||
|
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||||
|
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||||
|
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||||
|
} MRC_CH_TIMING;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
|
||||||
|
} MRC_IP_TIMING;
|
||||||
|
|
||||||
|
///
|
||||||
|
/// Memory SMBIOS & OC Memory Data Hob
|
||||||
|
///
|
||||||
|
typedef struct {
|
||||||
|
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||||
|
UINT8 DimmId;
|
||||||
|
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||||
|
UINT16 MfgId;
|
||||||
|
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||||
|
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||||
|
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||||
|
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||||
|
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||||
|
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||||
|
UINT16 Speed; ///< The maximum capable speed of the device, in MHz
|
||||||
|
UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
|
||||||
|
} DIMM_INFO;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||||
|
UINT8 ChannelId;
|
||||||
|
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||||
|
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||||
|
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||||
|
} CHANNEL_INFO;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||||
|
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||||
|
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||||
|
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||||
|
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||||
|
} CONTROLLER_INFO;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
UINT64 BaseAddress; ///< Trace Base Address
|
||||||
|
UINT64 TotalSize; ///< Total Trace Region of Same Cache type
|
||||||
|
UINT8 CacheType; ///< Trace Cache Type
|
||||||
|
UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
|
||||||
|
UINT8 Rsvd[2];
|
||||||
|
} PSMI_MEM_INFO;
|
||||||
|
|
||||||
|
/// This data structure contains per-SaGv timing values that are considered output by the MRC.
|
||||||
|
typedef struct {
|
||||||
|
UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
|
||||||
|
MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
|
||||||
|
MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
|
||||||
|
} HOB_SAGV_TIMING_OUT;
|
||||||
|
|
||||||
|
/// This data structure contains SAGV config values that are considered output by the MRC.
|
||||||
|
typedef struct {
|
||||||
|
UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
|
||||||
|
UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
|
||||||
|
HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
|
||||||
|
} HOB_SAGV_INFO;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
UINT8 Revision;
|
||||||
|
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||||
|
/** As defined in SMBIOS 3.0 spec
|
||||||
|
Section 7.18.2 and Table 75
|
||||||
|
**/
|
||||||
|
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||||
|
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||||
|
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||||
|
/** As defined in SMBIOS 3.0 spec
|
||||||
|
Section 7.17.3 and Table 72
|
||||||
|
**/
|
||||||
|
UINT8 ErrorCorrectionType;
|
||||||
|
|
||||||
|
SiMrcVersion Version;
|
||||||
|
BOOLEAN EccSupport;
|
||||||
|
UINT8 MemoryProfile;
|
||||||
|
UINT8 IsDMBRunning; ///< Deprecated.
|
||||||
|
UINT32 TotalPhysicalMemorySize;
|
||||||
|
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||||
|
///
|
||||||
|
/// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
|
||||||
|
/// Bit 0: XMP Profile 1 capability status
|
||||||
|
/// Bit 1: XMP Profile 2 capability status
|
||||||
|
/// Bit 2: XMP Profile 3 capability status
|
||||||
|
/// Bit 3: User Profile 4 capability status
|
||||||
|
/// Bit 4: User Profile 5 capability status
|
||||||
|
///
|
||||||
|
UINT8 XmpProfileEnable;
|
||||||
|
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
|
||||||
|
UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255
|
||||||
|
UINT8 RefClk;
|
||||||
|
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||||
|
UINT32 VddqVoltage[MAX_PROFILE_NUM];
|
||||||
|
UINT32 VppVoltage[MAX_PROFILE_NUM];
|
||||||
|
CONTROLLER_INFO Controller[MAX_NODE];
|
||||||
|
UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
|
||||||
|
UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
|
||||||
|
HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
|
||||||
|
UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
|
||||||
|
BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
|
||||||
|
BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
|
||||||
|
BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
|
||||||
|
} MEMORY_INFO_DATA_HOB;
|
||||||
|
|
||||||
|
/**
|
||||||
|
Memory Platform Data Hob
|
||||||
|
|
||||||
|
<b>Revision 1:</b>
|
||||||
|
- Initial version.
|
||||||
|
<b>Revision 2:</b>
|
||||||
|
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||||
|
**/
|
||||||
|
typedef struct {
|
||||||
|
UINT8 Revision;
|
||||||
|
UINT8 Reserved[3];
|
||||||
|
UINT32 BootMode;
|
||||||
|
UINT32 TsegSize;
|
||||||
|
UINT32 TsegBase;
|
||||||
|
UINT32 PrmrrSize;
|
||||||
|
UINT64 PrmrrBase;
|
||||||
|
UINT32 GttBase;
|
||||||
|
UINT32 MmioSize;
|
||||||
|
UINT32 PciEBaseAddress;
|
||||||
|
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
|
||||||
|
PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
|
||||||
|
BOOLEAN MrcBasicMemoryTestPass;
|
||||||
|
} MEMORY_PLATFORM_DATA;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||||
|
MEMORY_PLATFORM_DATA Data;
|
||||||
|
UINT8 *Buffer;
|
||||||
|
} MEMORY_PLATFORM_DATA_HOB;
|
||||||
|
|
||||||
|
#pragma pack (pop)
|
||||||
|
|
||||||
|
#endif // _MEM_INFO_HOB_H_
|
Loading…
Reference in New Issue