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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2003-11-09 23:29:42 +00:00
parent c8ea12d672
commit e3da4d3ce8
2 changed files with 20 additions and 3 deletions
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17
src/config/Options.lb
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@ -172,6 +172,11 @@ define CONFIG_CHIP_CONFIGURE
export used
comment "Use new chip_configure method for configuring (non-pci) devices"
end
define CONFIG_USE_INIT
default 0
export never
comment "Use stage 1 initialization code"
end
###############################################
# ROM image options
@ -532,6 +537,18 @@ define PCIC0_CFGDATA
export used
comment "PCI Configuration Data Register"
end
define PNP_CFGADDR
default none
format "0x%x"
export used
comment "PNP Configuration Address Register"
end
define PNP_CFGDATA
default none
format "0x%x"
export used
comment "PNP Configuration Data Register"
end
define UART0_IO_BASE
default none
format "0x%x"

6
src/cpu/ppc/ppc4xx/Config.lb
View File

@ -9,11 +9,11 @@ uses DCACHE_RAM_SIZE
##
## PPC4XX always uses cache ram for initial setup
##
option USE_DCACHE_RAM=1
default USE_DCACHE_RAM=1
## Set dcache ram above linuxbios image
option DCACHE_RAM_BASE=_RAMBASE+0x100000
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 16Kb
option DCACHE_RAM_SIZE=16384
default DCACHE_RAM_SIZE=16384
initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc
initobject cache.S