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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -172,6 +172,11 @@ define CONFIG_CHIP_CONFIGURE
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export used
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export used
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comment "Use new chip_configure method for configuring (non-pci) devices"
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comment "Use new chip_configure method for configuring (non-pci) devices"
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end
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end
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define CONFIG_USE_INIT
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default 0
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export never
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comment "Use stage 1 initialization code"
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end
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###############################################
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###############################################
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# ROM image options
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# ROM image options
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@ -532,6 +537,18 @@ define PCIC0_CFGDATA
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export used
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export used
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comment "PCI Configuration Data Register"
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comment "PCI Configuration Data Register"
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end
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end
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define PNP_CFGADDR
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default none
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format "0x%x"
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export used
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comment "PNP Configuration Address Register"
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end
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define PNP_CFGDATA
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default none
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format "0x%x"
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export used
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comment "PNP Configuration Data Register"
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end
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define UART0_IO_BASE
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define UART0_IO_BASE
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default none
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default none
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format "0x%x"
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format "0x%x"
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@ -9,11 +9,11 @@ uses DCACHE_RAM_SIZE
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##
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##
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## PPC4XX always uses cache ram for initial setup
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## PPC4XX always uses cache ram for initial setup
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##
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##
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option USE_DCACHE_RAM=1
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default USE_DCACHE_RAM=1
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## Set dcache ram above linuxbios image
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## Set dcache ram above linuxbios image
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option DCACHE_RAM_BASE=_RAMBASE+0x100000
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default DCACHE_RAM_BASE=_RAMBASE+0x100000
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## Dcache size is 16Kb
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## Dcache size is 16Kb
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option DCACHE_RAM_SIZE=16384
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default DCACHE_RAM_SIZE=16384
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initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc
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initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc
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initobject cache.S
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initobject cache.S
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