src: Get rid of unneeded whitespace

Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/arch/arm/include/armv7/arch/cache.h

@@ -48,8 +48,8 @@
 #define SCTLR_SW	(1 << 10)	/* SWP and SWPB enable		*/
 #define SCTLR_Z		(1 << 11)	/* Branch prediction enable	*/
 #define SCTLR_I		(1 << 12)	/* Instruction cache enable	*/
-#define SCTLR_V		(1 << 13)	/* Low/high exception vectors 	*/
-#define SCTLR_RR  	(1 << 14)	/* Round Robin select		*/
+#define SCTLR_V		(1 << 13)	/* Low/high exception vectors	*/
+#define SCTLR_RR	(1 << 14)	/* Round Robin select		*/
 /* Bits 16:15 are reserved */
 #define SCTLR_HA	(1 << 17)	/* Hardware Access flag enable	*/
 /* Bit 18 is reserved */

src/arch/arm64/include/armv8/arch/cache.h

@@ -48,8 +48,8 @@
 #define SCTLR_EL1_UMA	(1 << 9)	/* User mask access		*/
 #define SCTLR_EL1_DZE	(1 << 14)	/* DC ZVA instruction at EL0	*/
 #define SCTLR_EL1_UCT	(1 << 15)	/* CTR_EL0 register EL0 access	*/
-#define SCTLR_EL1_NTWI	(1 << 16)	/* Not trap WFI		 	*/
-#define SCTLR_EL1_NTWE	(1 << 18)	/* Not trap WFE		 	*/
+#define SCTLR_EL1_NTWI	(1 << 16)	/* Not trap WFI			*/
+#define SCTLR_EL1_NTWE	(1 << 18)	/* Not trap WFE			*/
 #define SCTLR_EL1_E0E	(1 << 24)	/* Exception endianness at EL0	*/
 #define SCTLR_EL1_UCI	(1 << 26)	/* EL0 access to cache instructions */
 

src/device/dram/ddr3.c

@@ -115,7 +115,7 @@ u16 spd_ddr3_calc_unique_crc(u8 *spd, int len)
  * array, and passed to this function.
  *
  * @param dimm pointer to @ref dimm_attr structure where the decoded data is to
- * 	       be stored
+ *	       be stored
  * @param spd array of raw data previously read from the SPD.
  *
  * @return @ref spd_status enumerator
@@ -123,7 +123,7 @@ u16 spd_ddr3_calc_unique_crc(u8 *spd, int len)
  *		SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD
  *		SPD_STATUS_CRC_ERROR -- CRC did not verify
  *		SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
- * 					    detected.
+ *					    detected.
  */
 int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
 {

src/lib/device_tree.c

@@ -497,12 +497,12 @@ void dt_read_cell_props(struct device_tree_node *node, u32 *addrcp, u32 *sizecp)
  *
  * @param parent	The node from which to start the relative path lookup.
  * @param path		An array of path component strings that will be looked
- * 			up in order to find the node. Must be terminated with
- * 			a NULL pointer. Example: {'firmware', 'coreboot', NULL}
+ *			up in order to find the node. Must be terminated with
+ *			a NULL pointer. Example: {'firmware', 'coreboot', NULL}
  * @param addrcp	Pointer that will be updated with any #address-cells
- * 			value found in the path. May be NULL to ignore.
+ *			value found in the path. May be NULL to ignore.
  * @param sizecp	Pointer that will be updated with any #size-cells
- * 			value found in the path. May be NULL to ignore.
+ *			value found in the path. May be NULL to ignore.
  * @param create	1: Create node(s) if not found. 0: Return NULL instead.
  * @return		The found/created node, or NULL.
  */

src/mainboard/amd/inagua/buildOpts.c

@@ -36,7 +36,7 @@
 
 /* Select the CPU socket type. */
 #define INSTALL_G34_SOCKET_SUPPORT		FALSE
-#define INSTALL_C32_SOCKET_SUPPORT 		FALSE
+#define INSTALL_C32_SOCKET_SUPPORT		FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT		FALSE
 #define INSTALL_S1G4_SOCKET_SUPPORT		FALSE
 #define INSTALL_ASB2_SOCKET_SUPPORT		FALSE
@@ -53,7 +53,7 @@
  */
 
 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT		TRUE
-#define BLDOPT_REMOVE_FAMILY_12_SUPPORT 	TRUE
+#define BLDOPT_REMOVE_FAMILY_12_SUPPORT		TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT		FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT		TRUE
 

src/mainboard/amd/parmer/buildOpts.c

@@ -155,8 +155,8 @@
 #if IS_ENABLED(CONFIG_GFXUMA)
 #define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
 #define BLDCFG_UMA_ALLOCATION_MODE		  UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE      	  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
-#define BLDCFG_UMA_ALLOCATION_SIZE      	  0x2000//512M
+//#define BLDCFG_UMA_ALLOCATION_SIZE		  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE		  0x2000//512M
 #define BLDCFG_UMA_ABOVE4G_SUPPORT                FALSE
 #endif
 

src/mainboard/lenovo/t400/devicetree.cb

@@ -237,7 +237,7 @@ chip northbridge/intel/gm45
 			device pci 1f.3 on # SMBus
 				subsystemid 0x17aa 0x20f9
 				ioapic_irq 2 INTC 0x12
-			 	# eeprom, 8 virtual devices, same chip
+				# eeprom, 8 virtual devices, same chip
 				chip drivers/i2c/at24rf08c
 					device i2c 54 on end
 					device i2c 55 on end

src/mainboard/msi/ms7721/buildOpts.c

@@ -170,8 +170,8 @@
 #if IS_ENABLED(CONFIG_GFXUMA)
 #define BLDCFG_UMA_ALIGNMENT			UMA_4MB_ALIGNED
 #define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE	  	0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
-#define BLDCFG_UMA_ALLOCATION_SIZE	  	0x2000//512M
+//#define BLDCFG_UMA_ALLOCATION_SIZE		0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000//512M
 #define BLDCFG_UMA_ABOVE4G_SUPPORT		FALSE
 #endif
 

src/mainboard/pcengines/apu2/romstage.c

@@ -74,8 +74,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Load MPB */
 	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
 	AGESAWRAPPER(amdinitreset);

src/southbridge/intel/ibexpeak/smi.c

@@ -325,7 +325,7 @@ void southbridge_clear_smi_status(void)
 	reset_pm1_status();
 
 	/* Set EOS bit so other SMIs can occur. */
- 	smi_set_eos();
+	smi_set_eos();
 }
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)