mb/google/nissa/var/gothrax: Initialise overridetree
Add an initial overridetree for gothrax based on the schematic. BUG=b:274707912 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76013 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yunlong Jia
Subrata Banik
parent
92904bcdff
commit
e40cdd5ae4
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@ -26,6 +26,9 @@ static const struct pad_config override_gpio_table[] = {
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/* B6 : SOC_I2C_SUB_SCL */
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PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
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/* C1 : SMBDATA ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_C1, 1, DEEP),
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/* D3 : WCAM_RST_L */
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PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
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/* D15 : EN_PP2800_WCAM_X */
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@ -69,6 +72,11 @@ static const struct pad_config early_gpio_table[] = {
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* Enable touchscreen, hold in reset */
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/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_C1, 0, DEEP),
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/* H12 : UART0_RTS# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H12, 1, DEEP),
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/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
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@ -1,4 +1,28 @@
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fw_config
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field DB_USB 0 1
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option DB_NONE 0
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option DB_C_A 1
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option DB_C_LTE 2
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end
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field THERMAL_SOLUTION 2
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option THERMAL_SOLUTION_PASSIVE 0
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option THERMAL_SOLUTION_ACTIVE 1
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end
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field WLAN 3 4
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option WLAN_MT7921_AZUREWAVE 0
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option WLAN_AX211_Intel 1
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end
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field AUDIO 5 6
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option AUDIO_ALC1019_ALC5682IVS 0
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end
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field STYLUS 7
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option STYLUS_ABSENT 0
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option STYLUS_PRESENT 1
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end
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end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-42.3.7.
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@ -45,7 +69,397 @@ chip soc/intel/alderlake
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
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device domain 0 on
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end
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# Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
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# Bit 2 - C1 has a redriver which does SBU muxing.
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# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
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register "tcss_aux_ori" = "5"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
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register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
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# Configure external V1P05/Vnn/VnnSx Rails
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
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.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
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.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
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.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
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.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
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.v1p05_voltage_mv = 1050,
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.vnn_voltage_mv = 780,
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.vnn_sx_voltage_mv = 1050,
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.v1p05_icc_max_ma = 500,
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.vnn_icc_max_ma = 500,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C1 | Touchscreen |
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#| I2C2 | Sub-board(PSensor)/WCAM |
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#| I2C3 | Audio |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST_PLUS,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST_PLUS,
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.scl_lcnt = 55,
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.scl_hcnt = 30,
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.sda_hold = 7,
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}
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 160,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 157,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 157,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 152,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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}"
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device domain 0 on
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""Memory""
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register "options.tsr[1].desc" = ""Charger""
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register "options.tsr[2].desc" = ""Ambient""
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# TODO: below values are initial reference values only
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 6000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200
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},
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.pl2 = {
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.min_power = 25000,
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.max_power = 25000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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device generic 0 on end
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end
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end
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device ref i2c1 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "detect" = "1"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "reset_delay_ms" = "20"
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register "enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "enable_delay_ms" = "1"
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register "has_power_resource" = "1"
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device i2c 0x10 on end
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end
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end
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device ref i2c2 on
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chip drivers/i2c/sx9324
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register "desc" = ""SAR2 Proximity Sensor""
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
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register "speed" = "I2C_SPEED_FAST"
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register "uid" = "2"
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register "reg_gnrl_ctrl0" = "0x16"
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register "reg_gnrl_ctrl1" = "0x21"
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register "reg_afe_ctrl0" = "0x00"
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register "reg_afe_ctrl1" = "0x10"
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register "reg_afe_ctrl2" = "0x00"
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register "reg_afe_ctrl3" = "0x00"
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register "reg_afe_ctrl4" = "0x07"
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register "reg_afe_ctrl5" = "0x00"
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register "reg_afe_ctrl6" = "0x00"
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register "reg_afe_ctrl7" = "0x07"
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register "reg_afe_ctrl8" = "0x12"
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register "reg_afe_ctrl9" = "0x0f"
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register "reg_prox_ctrl0" = "0x12"
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register "reg_prox_ctrl1" = "0x12"
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register "reg_prox_ctrl2" = "0x90"
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register "reg_prox_ctrl3" = "0x60"
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register "reg_prox_ctrl4" = "0x0c"
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register "reg_prox_ctrl5" = "0x12"
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register "reg_prox_ctrl6" = "0x3c"
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register "reg_prox_ctrl7" = "0x58"
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register "reg_adv_ctrl0" = "0x00"
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register "reg_adv_ctrl1" = "0x00"
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register "reg_adv_ctrl2" = "0x00"
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register "reg_adv_ctrl3" = "0x00"
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register "reg_adv_ctrl4" = "0x00"
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register "reg_adv_ctrl5" = "0x05"
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register "reg_adv_ctrl6" = "0x00"
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register "reg_adv_ctrl7" = "0x00"
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register "reg_adv_ctrl8" = "0x00"
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register "reg_adv_ctrl9" = "0x00"
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register "reg_adv_ctrl10" = "0x5c"
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register "reg_adv_ctrl11" = "0x52"
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register "reg_adv_ctrl12" = "0xb5"
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register "reg_adv_ctrl13" = "0x00"
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register "reg_adv_ctrl14" = "0x80"
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register "reg_adv_ctrl15" = "0x0c"
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register "reg_adv_ctrl16" = "0x38"
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register "reg_adv_ctrl17" = "0x56"
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register "reg_adv_ctrl18" = "0x33"
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register "reg_adv_ctrl19" = "0xf0"
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register "reg_adv_ctrl20" = "0xf0"
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device i2c 28 on end
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end
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end
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device ref i2c3 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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chip drivers/generic/alc1015
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register "hid" = ""RTL1019""
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register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
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device generic 0 on end
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end
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end
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device ref i2c5 on
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chip drivers/i2c/hid
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register "generic.hid" = ""PNP0C50""
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register "generic.desc" = ""PIXART Touchpad""
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register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "generic.wake" = "GPE0_DW2_14"
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register "generic.detect" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 15 on end
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end
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end
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device ref pcie_rp4 on
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# PCIe 4 WLAN
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register "pch_pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip drivers/wifi/generic
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register "wake" = "GPE0_DW1_03"
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register "add_acpi_dma_property" = "true"
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device pci 00.0 on end
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end
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end
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device ref pcie_rp7 on
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# Enable SD Card PCIe 7 using clk 3
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port2 on end
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end
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end
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end
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end
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device ref xhci on
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
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device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 UFC""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WFC""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""CNVi Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue