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nb/intel/haswell: Move register headers into a subfolder 

Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-09-14 15:47:59 +02:00
parent b8b117c7e7
commit e4156c33bd
3 changed files with 8 additions and 8 deletions
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4
src/northbridge/intel/haswell/haswell.h
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@ -18,7 +18,7 @@
/* Device 0:0.0 PCI configuration space (Host Bridge) */ /* Device 0:0.0 PCI configuration space (Host Bridge) */
#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define HOST_BRIDGE PCI_DEV(0, 0, 0)
#include "hostbridge_regs.h" #include "registers/host_bridge.h"
/* Device 0:2.0 PCI configuration space (Graphics Device) */ /* Device 0:2.0 PCI configuration space (Graphics Device) */
@ -43,7 +43,7 @@
#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
/* As there are many registers, define them on a separate file */ /* As there are many registers, define them on a separate file */
#include "mchbar_regs.h" #include "registers/mchbar.h"
#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
#define DMAR_LCKDN (1 << 31) #define DMAR_LCKDN (1 << 31)

6
src/northbridge/intel/haswell/hostbridge_regs.h → src/northbridge/intel/haswell/registers/host_bridge.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __HASWELL_HOSTBRIDGE_REGS_H__ #ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__
#define __HASWELL_HOSTBRIDGE_REGS_H__ #define __HASWELL_REGISTERS_HOST_BRIDGE_H__
#define EPBAR 0x40 #define EPBAR 0x40
#define MCHBAR 0x48 #define MCHBAR 0x48
@ -68,4 +68,4 @@
#define CAPID0_B 0xe8 #define CAPID0_B 0xe8
#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */ #endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */

6
src/northbridge/intel/haswell/mchbar_regs.h → src/northbridge/intel/haswell/registers/mchbar.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __HASWELL_MCHBAR_REGS_H__ #ifndef __HASWELL_REGISTERS_MCHBAR_H__
#define __HASWELL_MCHBAR_REGS_H__ #define __HASWELL_REGISTERS_MCHBAR_H__
/* Register definitions */ /* Register definitions */
#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */
@ -44,4 +44,4 @@
#define DMIVCLIM 0x7000 #define DMIVCLIM 0x7000
#define CRDTLCK 0x77fc #define CRDTLCK 0x77fc
#endif /* __HASWELL_MCHBAR_REGS_H__ */ #endif /* __HASWELL_REGISTERS_MCHBAR_H__ */