nb/intel/haswell: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -18,7 +18,7 @@
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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#include "hostbridge_regs.h"
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#include "registers/host_bridge.h"
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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@ -43,7 +43,7 @@
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#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
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/* As there are many registers, define them on a separate file */
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#include "mchbar_regs.h"
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#include "registers/mchbar.h"
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#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
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#define DMAR_LCKDN (1 << 31)
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __HASWELL_HOSTBRIDGE_REGS_H__
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#define __HASWELL_HOSTBRIDGE_REGS_H__
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#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__
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#define __HASWELL_REGISTERS_HOST_BRIDGE_H__
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#define EPBAR 0x40
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#define MCHBAR 0x48
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@ -68,4 +68,4 @@
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#define CAPID0_B 0xe8
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#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */
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#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __HASWELL_MCHBAR_REGS_H__
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#define __HASWELL_MCHBAR_REGS_H__
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#ifndef __HASWELL_REGISTERS_MCHBAR_H__
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#define __HASWELL_REGISTERS_MCHBAR_H__
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/* Register definitions */
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#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */
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#define DMIVCLIM 0x7000
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#define CRDTLCK 0x77fc
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#endif /* __HASWELL_MCHBAR_REGS_H__ */
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#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */
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