vendorcode/intel/fsp/fsp2_0/skylake_sp: update header files
Added definitions in FspmUpd.h. Added gpio_fsp.h file which has definitions needed by mainboard gpio header file, to set gpio configuration through FSP-M UPD. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: I72727952685b5e453f4cde6c2e7e7fc7114c6884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
This commit is contained in:
Jonathan Zhang
Patrick Georgi
parent
e0060a80f0
commit
e425a09d6a
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@ -45,6 +45,51 @@ are permitted provided that the following conditions are met:
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#define MAX_CHANNEL 6 /* Maximum Number of Memory Channels */
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#define MAX_DIMM 2 /* Maximum Number of DIMMs per Channel */
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#define HIDE 1
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#define NOT_HIDE 0
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#define IIO_BIFURCATE_AUTO 0xFF
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/* Ports 1D-1A, 2D-2A, 3D-3A */
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#define IIO_BIFURCATE_x4x4x4x4 0
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#define IIO_BIFURCATE_x4x4xxx8 1
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#define IIO_BIFURCATE_xxx8x4x4 2
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#define IIO_BIFURCATE_xxx8xxx8 3
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#define IIO_BIFURCATE_xxxxxx16 4
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#define IIO_BIFURCATE_xxxxxxxx 0xF
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typedef enum {
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IioPortA = 0,
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IioPortB = 1,
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IioPortC = 2,
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IioPortD = 3
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} IIO_PORTS;
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/**
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* Enums and Macro definitions needed for reference RVP and CRB
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* table declarations
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**/
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typedef enum {
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Iio_Socket0 = 0,
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Iio_Socket1,
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Iio_Socket2,
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Iio_Socket3,
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Iio_Socket4,
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Iio_Socket5,
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Iio_Socket6,
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Iio_Socket7
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} IIO_SOCKETS;
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typedef enum {
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Iio_Iou0 = 0,
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Iio_Iou1,
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Iio_Iou2,
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Iio_Mcp0,
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Iio_Mcp1,
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Iio_IouMax
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} IIO_IOUS;
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/**
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IIO PCIe Ports
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**/
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@ -0,0 +1,205 @@
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/**
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Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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**/
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#ifndef _GPIO_FSP_H_
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#define _GPIO_FSP_H_
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//
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// Below defines are based on GPIO_CONFIG structure fields
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//
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#define GPIO_CONF_PAD_MODE_MASK 0xF
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#define GPIO_CONF_PAD_MODE_BIT_POS 0
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#define GPIO_CONF_HOST_OWN_MASK 0x3
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#define GPIO_CONF_HOST_OWN_BIT_POS 0
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#define GPIO_CONF_DIR_MASK 0x7
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#define GPIO_CONF_DIR_BIT_POS 0
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#define GPIO_CONF_INV_MASK 0x18
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#define GPIO_CONF_INV_BIT_POS 3
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#define GPIO_CONF_OUTPUT_MASK 0x3
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#define GPIO_CONF_OUTPUT_BIT_POS 0
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#define GPIO_CONF_INT_ROUTE_MASK 0x1F
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#define GPIO_CONF_INT_ROUTE_BIT_POS 0
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#define GPIO_CONF_INT_TRIG_MASK 0xE0
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#define GPIO_CONF_INT_TRIG_BIT_POS 5
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#define GPIO_CONF_RESET_MASK 0x7
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#define GPIO_CONF_RESET_BIT_POS 0
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#define GPIO_CONF_TERM_MASK 0x1F
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#define GPIO_CONF_TERM_BIT_POS 0
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#define GPIO_CONF_PADTOL_MASK 0x60
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#define GPIO_CONF_PADTOL_BIT_POS 5
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#define GPIO_CONF_LOCK_MASK 0x7
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#define GPIO_CONF_LOCK_BIT_POS 0
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#define GPIO_CONF_RXRAW_MASK 0x3
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#define GPIO_CONF_RXRAW_BIT_POS 0
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typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT;
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///
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/// GPIO Pad Mode
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///
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typedef enum {
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GpioPadModeGpio = 0x1,
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GpioPadModeNative1 = 0x3,
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GpioPadModeNative2 = 0x5,
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GpioPadModeNative3 = 0x7,
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GpioPadModeNative4 = 0x9
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} GPIO_PAD_MODE;
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///
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/// Host Software Pad Ownership modes
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///
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typedef enum {
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GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
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GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI
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GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO
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} GPIO_HOSTSW_OWN;
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///
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/// GPIO Direction
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///
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typedef enum {
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GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
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GpioDirInOut =
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(0x1 | (0x1 << 3)), ///< Set pad for both output and input
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GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and
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///input with inversion
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GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
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GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
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GpioDirOut = 0x5, ///< Set pad for output only
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GpioDirNone = 0x7 ///< Disable both output and input
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} GPIO_DIRECTION;
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///
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/// GPIO Output State
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///
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typedef enum {
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GpioOutDefault = 0x0, ///< Leave output value unmodified
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GpioOutLow = 0x1, ///< Set output to low
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GpioOutHigh = 0x3 ///< Set output to high
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} GPIO_OUTPUT_STATE;
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///
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/// GPIO interrupt configuration
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/// This setting is applicable only if GPIO is in input mode.
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/// GPIO_INT_CONFIG allows to choose which interrupt is generated
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/// (IOxAPIC/SCI/SMI/NMI)
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/// and how it is triggered (edge or level).
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/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to
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/// GpioIntBothEdgecan
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/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel
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/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad.
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/// Not all GPIO are capable of generating an SMI or NMI interrupt
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///
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typedef enum {
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GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
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GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
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GpioIntNmi = 0x3, ///< Enable NMI interrupt only
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GpioIntSmi = 0x5, ///< Enable SMI interrupt only
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GpioIntSci = 0x9, ///< Enable SCI interrupt only
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GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
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GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
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GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of
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///edge depends on input inversion)
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GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
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GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
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} GPIO_INT_CONFIG;
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///
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/// GPIO Power Configuration
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/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified
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/// Pad Register fields).
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///
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typedef enum {
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GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified
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GpioResetPwrGood = 0x1, ///< Powergood reset
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GpioResetDeep = 0x3, ///< Deep GPIO Reset
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GpioResetNormal = 0x5, ///< GPIO Reset
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GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group)
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} GPIO_RESET_CONFIG;
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///
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/// GPIO Electrical Configuration
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/// Set GPIO termination and Pad Tolerance (applicable only for some pads)
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/// Field from GpioTermDefault to GpioTermNative can be OR'ed with
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/// GpioTolerance1v8.
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///
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typedef enum {
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GpioTermDefault = 0x0, ///< Leave termination setting unmodified
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GpioTermNone = 0x1, ///< none
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GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
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GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
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GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
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GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
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GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
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GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
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GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
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GpioTermNative = 0x1F, ///< Native function controls pads termination
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GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
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GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
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} GPIO_ELECTRICAL_CONFIG;
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///
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/// GPIO LockConfiguration
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/// Set GPIO configuration lock and output state lock
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/// GpioLockPadConfig and GpioLockOutputState can be OR'ed
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///
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typedef enum {
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GpioLockDefault = 0x0, ///< Leave lock setting unmodified
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GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
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GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
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} GPIO_LOCK_CONFIG;
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///
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/// Other GPIO Configuration
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/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions
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/// Supported settings:
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/// - RX raw override to '1' - allows to override input value to '1'
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/// This setting is applicable only if in input mode (both in GPIO and
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/// native usage).
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/// The override takes place at the internal pad state directly from buffer
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/// and before the RXINV.
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///
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typedef enum {
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GpioRxRaw1Default = 0x0, ///< Use default input override value
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GpioRxRaw1Dis = 0x1, ///< Don't override input
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GpioRxRaw1En = 0x3 ///< Override input to '1'
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} GPIO_OTHER_CONFIG;
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//
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// Possible values of Pad Ownership
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//
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typedef enum {
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GpioPadOwnHost = 0x0,
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GpioPadOwnCsme = 0x1,
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GpioPadOwnIsh = 0x2,
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} GPIO_PAD_OWN;
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#endif
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