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smaug: Increase drive strength for QSPI Pinmux 

Change the drive strength for QSPI Pinmux to DRIVE_STRENGTH_2 as per
recommendations from nVidia hardware engineers.

BUG=chrome-os-partner:41877
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt

Change-Id: I5a7b94acb57bbc21d277a49fd0a6b892638fc0ca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58d085e6acbcd0fd355b1c7efc10606312caf8e8
Original-Change-Id: I03dd288d2e335d40c83feaec7efbf10a7d3bf1e6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284959
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10945
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh 2015-07-13 09:46:56 -07:00 committed by Patrick Georgi
parent 0aa1d50be7
commit e431ab9c84
1 changed files with 10 additions and 6 deletions
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16
src/mainboard/google/smaug/bootblock.c
View File

@ -42,12 +42,16 @@ static const struct pad_config pmic_pads[] = {
/********************** SPI Flash *****************************/ /********************** SPI Flash *****************************/
static const struct pad_config spiflash_pads[] = { static const struct pad_config spiflash_pads[] = {
/* QSPI fLash: mosi, miso, clk, cs0, hold, wp */ /* QSPI fLash: mosi, miso, clk, cs0, hold, wp */
PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI), PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI), PINMUX_DRIVE_2X, QSPI),
PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE, QSPI), PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE, QSPI), PINMUX_DRIVE_2X, QSPI),
PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI), PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE | PINMUX_DRIVE_2X, QSPI),
PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI), PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE | PINMUX_DRIVE_2X, QSPI),
PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
PINMUX_DRIVE_2X, QSPI),
PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP |
PINMUX_DRIVE_2X, QSPI),
}; };
/********************* TPM ************************************/ /********************* TPM ************************************/