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soc/amd/picasso: Add data fabric register definitions 

These are used to setup the data fabric.

Definitions came from 55570-B1 Rev 3.14 - PPR for AMD Family 17h Model 18h

BUG=b:147042464

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib51f6e2fd304da9948d6625608af71f25b974854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41266
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2020-05-07 15:19:53 -06:00 committed by Patrick Georgi
parent b1ffca3057
commit e44651b496
1 changed files with 27 additions and 0 deletions
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27
src/soc/amd/picasso/include/soc/data_fabric.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_PICASSO_DATAFABRIC_H__
#define __SOC_PICASSO_DATAFABRIC_H__
#include <types.h>
/* D18F0 - Fabric Configuration registers */
#define IOMS0_FABRIC_ID 9
#define D18F0_VGAEN 0x80
#define VGA_ADDR_ENABLE BIT(0)
#define D18F0_MMIO_BASE0 0x200
#define D18F0_MMIO_LIMIT0 0x204
#define D18F0_MMIO_SHIFT 16
#define D18F0_MMIO_CTRL0 0x208
#define MMIO_NP BIT(12)
#define MMIO_DST_FABRIC_ID_SHIFT 4
#define MMIO_WE BIT(1)
#define MMIO_RE BIT(0)
#define NUM_NB_MMIO_REGS 8
#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0)
#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0)
#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0)
#endif /* __SOC_PICASSO_DATAFABRIC_H__ */