soc/amd/picasso: Add data fabric register definitions
These are used to setup the data fabric. Definitions came from 55570-B1 Rev 3.14 - PPR for AMD Family 17h Model 18h BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib51f6e2fd304da9948d6625608af71f25b974854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41266 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_PICASSO_DATAFABRIC_H__
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#define __SOC_PICASSO_DATAFABRIC_H__
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#include <types.h>
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/* D18F0 - Fabric Configuration registers */
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#define IOMS0_FABRIC_ID 9
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#define D18F0_VGAEN 0x80
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#define VGA_ADDR_ENABLE BIT(0)
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#define D18F0_MMIO_BASE0 0x200
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#define D18F0_MMIO_LIMIT0 0x204
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#define D18F0_MMIO_SHIFT 16
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#define D18F0_MMIO_CTRL0 0x208
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#define MMIO_NP BIT(12)
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#define MMIO_DST_FABRIC_ID_SHIFT 4
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#define MMIO_WE BIT(1)
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#define MMIO_RE BIT(0)
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#define NUM_NB_MMIO_REGS 8
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#define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0)
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#define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0)
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#define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0)
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#endif /* __SOC_PICASSO_DATAFABRIC_H__ */
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